Reliability assessment of flip-chip assemblies with lead-free solder joints

2003 ◽  
Author(s):  
A. Schubert ◽  
R. Dudek ◽  
H. Walter ◽  
E. Jung ◽  
A. Gollhardt ◽  
...  
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Reliability Assessment ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Failure mechanism of lead-free solder joints in flip chip packages

2002 ◽  
Vol 31 (11) ◽  
pp. 1256-1263 ◽  
Author(s):  
Fan Zhang ◽  
Ming Li ◽  
Bavani Balakrisnan ◽  
William T. Chen
Keyword(s):  
Failure Mechanism ◽  
Flip Chip ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach

2004 ◽  
Vol 44 (12) ◽  
pp. 1947-1955 ◽  
Author(s):  
D.G. Yang ◽  
J.S. Liang ◽  
Q.Y. Li ◽  
L.J. Ernst ◽  
G.Q. Zhang
Keyword(s):  
Parametric Study ◽  
Flip Chip ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping

2011 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
Solder Joints ◽  
Ceramic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Interconnects ◽  
Die Stress ◽  
Free Solder ◽  
Test Chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

Application of Finite Element Method in Optimal Design of Flip-Chip Package

2011 ◽  
Vol 264-265 ◽  
pp. 1660-1665
Author(s):  
Yong Cheng Lin ◽  
Yu Chi Xia
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Thermal Fatigue ◽  
Flip Chip ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

More and more solder joints in circuit boards and electronic products are changing to lead free solder, placing an emphasis on lead free solder joint reliability. Solder joint fatigue failure is a serious reliability concern in area array technologies. In this study, the effects of substrate materials on the solder joint thermal fatigue life were investigated by finite element model. Accelerated temperature cycling loading was imposed to evaluate the reliability of solder joints. The thermal strain/stress in solder joints of flip chip assemblies with different substrates was compared, and the fatigue life of solder joints were evaluated by Darveaux’s crack initiation and growth model. The results show the mechanisms of substrate flexibility on improving solder joint thermal fatigue.

Numerical Investigation on Electromigration Oriented Failure of Lead Free Solder Joints With Aging Effects

2019 ◽  
Author(s):  
Tusher Ahmed ◽  
Mohammad Motalab ◽  
Jeffrey C. Suhling
Keyword(s):  
Thermal Aging ◽  
Flip Chip ◽  
Solder Joints ◽  
Mass Diffusion ◽  
Lead Free ◽  
Small Scale ◽  
Time To Failure ◽  
Lead Free Solder ◽  
Aging Effects ◽  
Free Solder

Abstract Lead free solder materials have replaced lead based solder materials nowadays for increased environmental concern. Further miniaturization of electronic solder joints in packages has caused electromigration to dominate among all the reliability issues found in electronic packages. This current investigation deals with the review of mechanical property degradations of SAC305(Sn-96.5Ag-3.0Cu-0.5) solder materials due to thermal aging and their effects on electromigration oriented failure of small scale flip chip solder bumps. Thermal aging causes significant degradation of ultimate strength as well as elastic modulus of the SAC solder material. This degradation in stress-strain relationship plays an utterly important role in electromigration oriented mass diffusion and subsequent failure in the solder joints. This research highlights the linkage between thermal aging oriented strength degradation and its effect on electromigration oriented void propagation rate and time to failure. Structural-electric diffusion analyses with a finite element analysis software have been performed and results derived from different aging conditions (1 to 60 days of aging at 100 °C) at different electromigration temperatures have revealed that mass diffusion due to electromigration and associated stress migration actually reduces with the increment of aging time and thus increases time to failure in case of a flip chip solder joint. Simulation results have been found to be in good agreement with the experimental results available in literatures. These results can pave way to further detailed experimental investigation on effect of thermal aging on electromigration.

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