Test Structure with Variable Test Data Width of IP Cores for Multicore SoCs with DVS and Multiple Voltage Islands

2016 ◽  
Author(s):  
Deng Libao ◽  
Wang Sha ◽  
Jin Chengyu ◽  
Hu Cong
Keyword(s):  
Test Data ◽  
Test Structure ◽  
Ip Cores ◽  
Voltage Islands

Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs

2005 ◽  
Vol 152 (6) ◽  
pp. 704 ◽  
Author(s):  
L. Li ◽  
K. Chakrabarty ◽  
S. Kajihara ◽  
S. Swaminathan
Keyword(s):  
Test Data ◽  
Testing Time ◽  
Data Volume ◽  
Ip Cores

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

2008 ◽  
Vol 16 (7) ◽  
pp. 926-931 ◽  
Author(s):  
Xrysovalantis Kavousianos ◽  
Emmanouil Kalligeros ◽  
Dimitris Nikolos
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
Multiple Scan ◽  
Scan Chains ◽  
Ip Cores

scholarly journals Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Usha S. Mehta ◽  
Kankar S. Dasgupta ◽  
Niranjan M. Devashrayee
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Peak Power ◽  
Test Data Compression ◽  
Test Power ◽  
Current Generation ◽  
Run Length ◽  
Coding Schemes ◽  
Entropy Bounds ◽  
Ip Cores

The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for “don't care” bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s.

Power-Aware Test Data Compression for Embedded IP Cores

2006 ◽  
Author(s):  
N. Badereddine ◽  
Z. Wang ◽  
P. Girard ◽  
K. Chakrabarty ◽  
S. Pravossoudovitch ◽  
...  
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
Ip Cores

scholarly journals Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-8 ◽  
Author(s):  
Usha Mehta ◽  
K. S. Dasgupta ◽  
N. M. Devashrayee
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Hamming Distance ◽  
Test Data Compression ◽  
Test Power ◽  
Silicon Area ◽  
Difference Vector ◽  
Run Length ◽  
Area Overhead ◽  
Ip Cores

Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reordering” which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed “Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)” is a modification to earlier proposed “Hamming Distance based Reordering—Columnwise Bit Filling and Difference vector.” This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.

scholarly journals A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

2018 ◽  
Vol 12 (3) ◽  
pp. 933
Author(s):  
Sanjoy Mitra ◽  
Debaprasad Das
Keyword(s):  
Test Data ◽  
Structural Information ◽  
Huffman Coding ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Hamming Codes ◽  
Efficient Test ◽  
Data Volume ◽  
Ip Cores ◽  
Test Vectors

As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.

Sign in / Sign up

Export Citation Format

Share Document