Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs

2005 ◽  
Vol 152 (6) ◽  
pp. 704 ◽  
Author(s):  
L. Li ◽  
K. Chakrabarty ◽  
S. Kajihara ◽  
S. Swaminathan
Keyword(s):  
Test Data ◽  
Testing Time ◽  
Data Volume ◽  
Ip Cores

scholarly journals A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

2018 ◽  
Vol 12 (3) ◽  
pp. 933
Author(s):  
Sanjoy Mitra ◽  
Debaprasad Das
Keyword(s):  
Test Data ◽  
Structural Information ◽  
Huffman Coding ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Hamming Codes ◽  
Efficient Test ◽  
Data Volume ◽  
Ip Cores ◽  
Test Vectors

As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.

Test Data Generation and Selection Using Levy Flight-Based Firefly Algorithm

2021 ◽  
Vol 9 (2) ◽  
pp. 18-34
Author(s):  
Abhishek Pandey ◽  
Soumya Banerjee
Keyword(s):  
Test Data ◽  
Firefly Algorithm ◽  
Optimization Problem ◽  
Structural Testing ◽  
Software Test ◽  
Testing Time ◽  
Test Data Generation ◽  
Data Generation ◽  
Test Suite Optimization ◽  
Test Optimization

This article discusses the application of an improved version of the firefly algorithm for the test suite optimization problem. Software test optimization refers to optimizing test data generation and selection for structural testing criteria for white box testing. This will subsequently reduce the two most costly activities performed during testing: time and cost. Recently, various search-based approaches proved very interesting results for the software test optimization problem. Also, due to no free lunch theorem, scientists are continuously searching for more efficient and convergent methods for the optimization problem. In this paper, firefly algorithm is modified in a way that local search ability is improved. Levy flights are incorporated into the firefly algorithm. This modified algorithm is applied to the software test optimization problem. This is the first application of Levy-based firefly algorithm for software test optimization. Results are shown and compared with some existing metaheuristic approaches.

scholarly journals Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

2021 ◽  
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Test Data ◽  
Dynamic Reconfiguration ◽  
Experimental Results ◽  
Testing Time ◽  
Industrial Testing ◽  
Difficult Condition ◽  
Optimization Methodology ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

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