Low power testing - What can commercial DFT tools provide?

2011 International Green Computing Conference and Workshops ◽

10.1109/igcc.2011.6008609 ◽

2011 ◽

Author(s):

Xijiang Lin

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing

Download Full-text

Low Power Testing based on MOS Design Modified Flip-Flop

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i29/91653 ◽

2016 ◽

Vol 9 (29) ◽

Author(s):

Anjali Chava ◽

S. Saravanan

Keyword(s):

Low Power ◽

Flip Flop ◽

Low Power Testing ◽

Power Testing

Download Full-text

A new BIST structure for low power testing

2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 ◽

10.1109/icasic.2003.1277425 ◽

2003 ◽

Cited By ~ 3

Author(s):

Li Jie ◽

Yang Jun ◽

Li Rui ◽

Wang Chao

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing

Download Full-text

An efficient test vector ordering method for low power testing

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339559 ◽

2004 ◽

Cited By ~ 5

Author(s):

X. Kavousianos ◽

D. Bakalis ◽

M. Bellos ◽

D. Nikolos

Keyword(s):

Low Power ◽

Test Vector ◽

Low Power Testing ◽

Efficient Test ◽

Power Testing

Download Full-text

Is Low Power Testing Necessary? What does the Test Industry Truly Need?

2009 Asian Test Symposium ◽

10.1109/ats.2009.91 ◽

2009 ◽

Author(s):

Anis Uzzaman

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing

Download Full-text

Low power testing using re-configurable Johnson counter and scalable SIC counter

2015 International Conference on Communications and Signal Processing (ICCSP) ◽

10.1109/iccsp.2015.7322754 ◽

2015 ◽

Author(s):

Pallavi Margade

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing

Download Full-text

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.72 ◽

2005 ◽

Author(s):

H. Esmaeilzadeh ◽

S. Shamshiri ◽

P. Saeedi ◽

Z. Navabi

Keyword(s):

Low Power ◽

Low Power Testing ◽

Cell Architecture ◽

Power Testing

Download Full-text

Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing

IET Computers & Digital Techniques ◽

10.1049/iet-cdt:20060114 ◽

2007 ◽

Vol 1 (4) ◽

pp. 369 ◽

Cited By ~ 7

Author(s):

M.-H. Yang ◽

Y. Kim ◽

Y. Park ◽

D. Lee ◽

S. Kang

Keyword(s):

Low Power ◽

Shift Register ◽

Linear Feedback Shift Register ◽

Linear Feedback ◽

Low Power Testing ◽

Feedback Shift Register ◽

Self Test ◽

Built In Self Test ◽

Power Testing

Download Full-text

Comprehensive study of the operating and testing experience during the startup and initial operation at the Fort St. Vrain HTGR. Phase 2. Core loading, physics, and low power testing

10.2172/5027135 ◽

1978 ◽

Author(s):

K. R. Van Howe ◽

M. H. Raudenbush

Keyword(s):

Low Power ◽

Phase 2 ◽

Initial Operation ◽

Low Power Testing ◽

Power Testing ◽

Comprehensive Study

Download Full-text

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

IEICE Transactions on Information and Systems ◽

10.1093/ietisy/e88-d.9.2126 ◽

2005 ◽

Vol E88-D (9) ◽

pp. 2126-2134 ◽

Cited By ~ 3

Author(s):

Y. HAN

Keyword(s):

Low Power ◽

Low Power Testing ◽

Embedded Cores ◽

Scan Chains ◽

Power Testing

Download Full-text

Jump scan: a DFT technique for low power testing

23rd IEEE VLSI Test Symposium (VTS'05) ◽

10.1109/vts.2005.51 ◽

2005 ◽

Cited By ~ 18

Author(s):

Min-Hao Chiu ◽

J.C.-M. Li

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing

Download Full-text