NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis

2006 ◽  
Author(s):  
Xinyu Li ◽  
Omar Hammami
Keyword(s):  
Principal Component Analysis ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Principal Component ◽  
Component Analysis ◽  
Network On Chip ◽  
Chip Design ◽  
On Chip ◽  
Direct Execution

Structural Design Space Exploration Using Principal Component Analysis

2020 ◽  
Vol 20 (6) ◽  
Author(s):  
Spencer Bunnell ◽  
Steven Gorrell ◽  
John Salmon ◽  
Christopher Thelin ◽  
Christopher Ruoti
Keyword(s):  
Principal Component Analysis ◽  
Structural Design ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Principal Component ◽  
Component Analysis ◽  
Compressor Blades ◽  
Design Variables ◽  
Stress Changes

Abstract Design space exploration (DSE) is the process whereby a designer seeks to understand some results across a set of design variations. Structural DSE of turbomachinery compressor blades is often challenging because the large number of design variables make it difficult to learn the effect that each variable has upon the stress contours. Principal component analysis (PCA) of the stress contours is used as a way to understand how the stress contours change over the design space. Two methods are introduced to address the challenge of understanding how the stress changes over a large number of variables. First, a two-point correlation is applied to relate the design variables to the scores of each principal component. Second, a coupling of the stress and coordinate location of each node in PCA is developed which also indicates how the stress variations relate to geometric variations. These provide insight to how design variables influence the stress. It is shown how these methods use PCA as DSE tools to better explore the structural design space of compressor blades. Better DSE can improve compressor blades and the computational cost needed for their design.

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

Sign in / Sign up

Export Citation Format

Share Document