High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

2006 ◽  
Author(s):  
Krishna C. Saraswat ◽  
Chi On Chui ◽  
Donghyun Kim ◽  
Tejas Krishnamohan ◽  
Abhijit Pethe
Keyword(s):  
High Performance ◽  
High Mobility ◽  
Novel Device ◽  
Device Structures ◽  
Nanoscale Mosfets

A ROOM TEMPERATURE BALLISTIC DEFLECTION TRANSISTOR FOR HIGH PERFORMANCE APPLICATIONS

2009 ◽  
Vol 19 (01) ◽  
pp. 23-31 ◽  
Author(s):  
QUENTIN DIDUCK ◽  
HIROSHI IRIE ◽  
MARTIN MARGALA
Keyword(s):  
High Performance ◽  
Room Temperature ◽  
Ballistic Transport ◽  
High Mobility ◽  
Mean Free Path ◽  
Material System ◽  
Novel Device ◽  
Ballistic Electron ◽  
Ballistic Deflection Transistor ◽  
Channel Separation

The Ballistic Deflection Transistor (BDT) is a novel device that is based upon an electron steering and a ballistic deflection effect. Composed of an InGaAs - InAlAs heterostructure on an InP substrate, this material system provides a large mean free path and high mobility to support ballistic transport at room temperature. The planar nature of the device enables a two step lithography process, as well, implies a very low capacitance design. This transistor is unique in that no doping junction or barrier structure is employed. Rather, the transistor utilizes a two-dimensional electron gas (2DEG) to achieve ballistic electron transport in a gated microstructure, combined with asymmetric geometrical deflection. Motivated by reduced transit times, the structure can be operated such that current never stops flowing, but rather is only directed toward one of two output drain terminals. The BDT is unique in that it possesses both a positive and negative transconductance region. Experimental measurements have indicated that the transconductance of the device increases with applied drain-source voltage. DC measurements of prototype devices have verified small signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for higher transconductance through scaling. The six terminal device enables a normally differential mode of operation, and provides two drain outputs. These outputs, depending on gate bias, are either complementary or non-complementary. This facilitates a wide variety of circuit design techniques. Given the ultralow capacitive design, initial estimates of ft, for the device fabricated with a 430nm gate width, are over a THz.

PERFORMANCE LIMITATIONS OF Si CMOS AND ALTERNATIVES FOR NANOELECTRONICS

2006 ◽  
Vol 16 (01) ◽  
pp. 175-192 ◽  
Author(s):  
KRISHNA C. SARASWAT ◽  
CHI ON CHUI ◽  
PAWAN KAPUR ◽  
TEJAS KRISHNAMOHAN ◽  
AMMAR NAYFEH ◽  
...  
Keyword(s):  
Three Dimensional ◽  
High Mobility ◽  
Significant Rise ◽  
Vlsi Circuits ◽  
High Resistivity ◽  
Strained Si ◽  
Novel Device ◽  
Operation Temperature ◽  
Cross Section Area ◽  
Device Structures

It is believed that below the 65-nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge , high-k gate dielectrics and metal gate electrodes. Continuous scaling of VLSI circuits can pose significant problems for interconnects. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu . As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. We focus on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiple active Si layers. Heterogeneous integration of the new structures and materials on Si may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.

CHASSIS DESIGN & PERFORMANCE ANALYSIS FOR THE EUROPEAN EXOMARS ROVER

2005 ◽  
Vol 29 (4) ◽  
pp. 507-517
Author(s):  
Alex Ellery ◽  
Lutz Richter ◽  
Reinhold Bertrand
Keyword(s):  
Performance Analysis ◽  
Weight Distribution ◽  
High Performance ◽  
High Mobility ◽  
Scientific Instrument ◽  
Equal Weight ◽  
Scientific Instruments ◽  
Design Issues ◽  
Martian Surface ◽  
Considerable Size

The European Space Agency’s (ESA) ExoMars rover has recently been subject to a Phase A study led by EADS Astrium, UK. This rover mission represents a highly ambitious venture in that the rover is of considerable size ~200+kg with high mobility carrying a highly complex scientific instrument suite (Pasteur) of up to 40 kg in mass devoted to exobiological investigation of the Martian surface and sub-surface. The chassis design has been a particular challenge given the inhospitable terrain on Mars and the need to traverse such terrain robustly in order to deliver the scientific instruments to science targets of exobiological interest, We present some of the results and design issues encountered during the Phase A study related to the chassis. In particular, we have focussed on the overall tractive performance of a number of candidate chassis designs and selected the RCL (Science & Technology Rover Company Ltd in Russian) concept C design as the baseline option in terms of high performance with minimal mechanical complexity overhead. This design is a six-wheeled double-rocker bogie design to provide springless suspension and maintain approximately equal weight distribution across each wheel.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Quaternisation-polymerized N-type polyelectrolytes: synthesis, characterisation and application in high-performance polymer solar cells

2017 ◽  
Vol 4 (1) ◽  
pp. 88-97 ◽  
Author(s):  
Zhicheng Hu ◽  
Rongguo Xu ◽  
Sheng Dong ◽  
Kai Lin ◽  
Jinju Liu ◽  
...  
Keyword(s):  
Solar Cells ◽  
High Performance ◽  
Polymer Solar Cells ◽  
High Mobility ◽  
High Performance Polymer

We design and synthesize a series of high-mobility n-type polyelectrolytes with different anions via quaternisation polymerisation, which can be utilized as thickness-insensitive electron-transporting materials for polymer solar cells.

Ge based high performance nanoscale MOSFETs

2005 ◽  
Vol 80 ◽  
pp. 15-21 ◽  
Author(s):  
Krishna C. Saraswat ◽  
Chi On Chui ◽  
Tejas Krishnamohan ◽  
Ammar Nayfeh ◽  
Paul McIntyre
Keyword(s):  
High Performance ◽  
Nanoscale Mosfets

scholarly journals Orthogonal Time Sequency Multiplexing Modulation

2021 ◽  
Author(s):  
Tharaj Thaj ◽  
Emanuele Viterbo
Keyword(s):  
Time Domain ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Performance ◽  
High Mobility ◽  
Low Complexity ◽  
Modulation Scheme ◽  
Frequency Space ◽  
Time Frequency ◽  
Single Carrier ◽  
The Time Domain

This paper proposes <i>orthogonal time sequency multiplexing</i> (OTSM), a novel single carrier modulation scheme based on the well known Walsh-Hadamard transform (WHT) combined with row-column interleaving, and zero padding (ZP) between blocks in the time-domain. The information symbols in OTSM are multiplexed in the delay and sequency domain using a cascade of time-division and Walsh-Hadamard (sequency) multiplexing. By using the WHT for transmission and reception, the modulation and demodulation steps do not require any complex multiplications. We then propose two low-complexity detectors: (i) a simpler non-iterative detector based on a single tap minimum mean square time-frequency domain equalizer and (ii) an iterative time-domain detector. We demonstrate, via numerical simulations, that the proposed modulation scheme offers high performance gains over orthogonal frequency division multiplexing (OFDM) and exhibits the same performance of orthogonal time frequency space (OTFS) modulation, but with lower complexity. In proposing OTSM, along with simple detection schemes, we offer the lowest complexity solution to achieving reliable communication in high mobility wireless channels, as compared to the available schemes published so far in the literature.

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