High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide

Author(s):  
H.J. Osten ◽  
J.P. Liu ◽  
P. Gaworzewski ◽  
E. Bugiel ◽  
P. Zaumseil
2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2001 ◽  
Vol 670 ◽  
Author(s):  
Ran Liu ◽  
Stefan Zollner ◽  
Peter Fejes ◽  
Rich Gregory ◽  
Shifeng Lu ◽  
...  

ABSTRACTRapid shrinking in device dimensions calls for replacement of SiO2 by new gate insulators in future generations of MOSFETs. Among many desirable properties, potential candidates must have a higher dielectric constant, low leakage current, and thermal stability against reaction or diffusion to ensure sharp interfaces with both the substrate Si and the gate metal (or poly-Si). Extensive characterization of such materials in thin-film form is crucial not only for selection of the alternative gate dielectrics and processes, but also for development of appropriate metrology of the high-k films on Si. This paper will report recent results on structural and compositional properties of thin film SrTiO3 and transition metal oxides (ZrO2and HfO2).


2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  

2013 ◽  
Vol 1561 ◽  
Author(s):  
Revathy Padmanabhan ◽  
Navakanta Bhat ◽  
S. Mohan ◽  
Y. Morozumi ◽  
Sanjeev Kaushal

ABSTRACTMetal-insulator-metal (MIM) capacitors for DRAM applications have been realized using TiO2/ZrO2/TiO2 (TZT) and AlO-doped TZT (TZAZT and TZAZAZT) dielectric stacks. High capacitance densities of about 46.6 fF/μm2 (for TZT stacks), 46.2 fF/μm2 (for TZAZT stacks), and 46.8 fF/μm2 (for TZAZAZT stacks) have been achieved. Low leakage current densities of about 4.9×10−8 A/cm2, 5.5×10−9 A/cm2, and 9.7×10−9 A/cm2 (at -1 V) have been obtained for TZT, TZAZT, and TZAZAZT stacks, respectively. We analyze the leakage current mechanisms at different electric field regimes, and compute the barrier heights. The effects of constant current stress and constant voltage stress on the device characteristics are studied, and excellent device reliability is demonstrated. We compare the device performance of the fabricated capacitors with other stacked high-k MIM capacitors reported in recent literature.


2003 ◽  
Vol 39 (8) ◽  
pp. 692 ◽  
Author(s):  
C.W. Yang ◽  
Y.K. Fang ◽  
S.F. Chen ◽  
M.F. Wang ◽  
T.H. Hou ◽  
...  

2012 ◽  
Vol 463-464 ◽  
pp. 1341-1345 ◽  
Author(s):  
Chong Liu ◽  
Xiao Li Fan

This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.


2007 ◽  
Vol 43 (21) ◽  
pp. 1130 ◽  
Author(s):  
A. Venkateshan ◽  
R. Singh ◽  
K.F. Poole ◽  
J. Harriss ◽  
H. Senter ◽  
...  

2019 ◽  
Vol 40 (4) ◽  
pp. 502-505 ◽  
Author(s):  
Tae In Lee ◽  
Hyun Jun Ahn ◽  
Min Ju Kim ◽  
Eui Joong Shin ◽  
Seung Hwan Lee ◽  
...  

2008 ◽  
Vol 1091 ◽  
Author(s):  
Cheng-Chin Liu ◽  
Kuo-Jui Chang ◽  
Feng-Yu Yang ◽  
Ta-Chuan Liao ◽  
Huang-Chung Cheng

AbstractWe have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.


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