Modifying Slots in Test Vectors to Validate Decoders of a Train Network

2006 ◽  
Author(s):  
Jaime Jimenez ◽  
Iker Hoyos ◽  
Jagoba Arias ◽  
Armando Astorlao ◽  
Jose L. Martin
Keyword(s):  
Test Vectors

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

2009 ◽  
Vol E92-A (12) ◽  
pp. 3128-3135
Author(s):  
Yoshinobu HIGAMI ◽  
Kewal K. SALUJA ◽  
Hiroshi TAKAHASHI ◽  
Shin-ya KOBAYASHI ◽  
Yuzo TAKAMATSU
Keyword(s):  
Defect Coverage ◽  
Test Vectors

A Combining FPE and Additional Test Vectors Hybrid Strategy for IPMSM Sensorless Control

2018 ◽  
Vol 33 (7) ◽  
pp. 6104-6113 ◽  
Author(s):  
Xin Luo ◽  
Qipeng Tang ◽  
Anwen Shen ◽  
Hanlin Shen ◽  
Jinbang Xu
Keyword(s):  
Sensorless Control ◽  
Additional Test ◽  
Hybrid Strategy ◽  
Test Vectors

scholarly journals Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

2021 ◽  
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Test Data ◽  
Dynamic Reconfiguration ◽  
Experimental Results ◽  
Testing Time ◽  
Industrial Testing ◽  
Difficult Condition ◽  
Optimization Methodology ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

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