A Novel Loop Filter Design for Phase-Locked Loops

2006 ◽  
Author(s):  
Y.S. Chou ◽  
W.L. Mao ◽  
Y.C. Chen ◽  
F.R. Chang
Keyword(s):  
Filter Design ◽  
Phase Locked Loops ◽  
Loop Filter

Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops

2012 ◽  
Vol 32 (3) ◽  
pp. 1013-1023 ◽  
Author(s):  
Yi-Bo Zhao ◽  
Chi-Kong Tse ◽  
Jiu-Chao Feng ◽  
Ye-Cai Guo
Keyword(s):  
Filter Design ◽  
Charge Pump ◽  
Phase Locked Loops ◽  
Loop Filter

scholarly journals Loop Filter Design for Phase-Locked Loops with Guaranteed Lock-in Range

2008 ◽  
Vol 41 (2) ◽  
pp. 6410-6415 ◽  
Author(s):  
Yung-Shan Chou ◽  
Yu-Cheng Chen ◽  
Fan-Ren Chang
Keyword(s):  
Filter Design ◽  
Phase Locked Loops ◽  
Loop Filter ◽  
Lock In

scholarly journals Modification of the loop filter design for a plucked string instrument

2012 ◽  
Vol 131 (2) ◽  
pp. EL126-EL132 ◽  
Author(s):  
Sangjin Cho ◽  
Hyungseob Han ◽  
Jongmyon Kim ◽  
Uipil Chong ◽  
Sangbock Cho
Keyword(s):  
Filter Design ◽  
Loop Filter ◽  
String Instrument

An estimator-predictor approach to PLL loop filter design

1990 ◽  
Vol 38 (10) ◽  
pp. 1667-1669 ◽  
Author(s):  
J.I. Statman ◽  
W.J. Hurd
Keyword(s):  
Filter Design ◽  
Loop Filter

scholarly journals Design an All Digital PLL with Ripple Reduction Technique

2019 ◽  
Vol 8 (10) ◽  
pp. 3164-3168
Keyword(s):  
Communication System ◽  
Frequency Synthesizer ◽  
Research Work ◽  
Feedback System ◽  
Reduction Technique ◽  
Phase Detector ◽  
Junction Temperature ◽  
Phase Locked Loops ◽  
Loop Filter ◽  
Ripple Reduction

The article describes about the design and implementation of advance version of Phase Lock Loop (PLL) is All Digital PLL. Research work is on ADPLL where parameter ripple is reduced by applying the technique of ripple reduction technique. Ripple reduction technique reduces the use of Kth counter, Kth counter comes under consideration when enable is ON. Phase locked loops are most widely used in communication system. Most of the PLL’s that are used currently are hybrid type PLL’s where all the blocks are assumed to be digital. The circuit design of ADPLL consists of Digital Controlled Oscillator (DCO), loop filter and Phase Frequency detector (PFD). Here phase detector used is Ex-or gate, for loop filter, Kth counter is used and Increment/Decrement circuit is used as DCO. Divide-by-N counter is used for feedback system. The output of the DCO is going in the PFD through the feedback network. Xilinx Vivado suit 2018.2 tools is used for simulating Verilog code. Board chosen in vivado is zed board Zynq. First, with the help of circuit diagram of ADPLL Verilog code is being written on project window. After compilation of code it is simulated with the help of test bench. After that it is going to be implemented and verified with the board zedboard. Number of LUTs used are 32 and Flip Flops used are 35. This paper presents an all digital approach for the design, simulation, synthesis and implementation of FPGA based ADPLL centered at 195.31 KHz using Verilog HDL code. The proposed design methodology resulted in reduction of ripple, power dissipation, junction temperature of board. Proposed research work further can be used in communication for frequency synthesizer. Any system whether it is from communication or digital etc ADPLL is common to use for ripple reduction at its output. So ADPLL is basic building block in any type of communication system.

Sign in / Sign up

Export Citation Format

Share Document