An estimator-predictor approach to PLL loop filter design

1990 ◽  
Vol 38 (10) ◽  
pp. 1667-1669 ◽  
Author(s):  
J.I. Statman ◽  
W.J. Hurd
Keyword(s):  
Filter Design ◽  
Loop Filter

scholarly journals Modification of the loop filter design for a plucked string instrument

2012 ◽  
Vol 131 (2) ◽  
pp. EL126-EL132 ◽  
Author(s):  
Sangjin Cho ◽  
Hyungseob Han ◽  
Jongmyon Kim ◽  
Uipil Chong ◽  
Sangbock Cho
Keyword(s):  
Filter Design ◽  
Loop Filter ◽  
String Instrument

scholarly journals Memristor-Based Loop Filter Design for Phase Locked Loop

2019 ◽  
Vol 9 (3) ◽  
pp. 24 ◽  
Author(s):  
Naheem Olakunle Adesina ◽  
Ashok Srivastava
Keyword(s):  
Power Consumption ◽  
Filter Design ◽  
High Reliability ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Silicon Area ◽  
Main Challenge ◽  
A Charge ◽  
Basic Features

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

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