A Double-Edge-Triggered Phase Frequency Detector for Low Jitter PLL

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings ◽

10.1109/icsict.2006.306542 ◽

2006 ◽

Cited By ~ 1

Author(s):

Yan-ping Zhou ◽

Zhi-qiang Lu ◽

Yi-zheng Ye

Keyword(s):

Phase Frequency Detector ◽

Double Edge ◽

Low Jitter ◽

Frequency Detector

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Low-jitter PLL based on symmetric phase-frequency detector technique

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-009-9326-6 ◽

2009 ◽

Vol 62 (1) ◽

pp. 23-27 ◽

Cited By ~ 2

Author(s):

Chen Yingmei ◽

Wang Zhigong ◽

Zhang Li

Keyword(s):

Phase Frequency Detector ◽

Low Jitter ◽

Frequency Detector ◽

Symmetric Phase

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A 3-PS dead-zone double-edge-checking phase-frequency detector with 4.78 GHZ operating frequencies

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. ◽

10.1109/apccas.2004.1413034 ◽

2005 ◽

Cited By ~ 1

Author(s):

Chien-Ping Chou ◽

Zhi-Ming Lin ◽

Jun-Da Chen

Keyword(s):

Dead Zone ◽

Phase Frequency Detector ◽

Double Edge ◽

Frequency Detector

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Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004. ◽

10.1109/iccdcs.2004.1393380 ◽

2005 ◽

Cited By ~ 13

Author(s):

K. Arshak ◽

O. Abubaker ◽

E. Jafer

Keyword(s):

High Speed ◽

Phase Frequency Detector ◽

Low Jitter ◽

Frequency Detector

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A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_19 ◽

2012 ◽

pp. 166-171 ◽

Cited By ~ 3

Author(s):

Manas Kumar Hati ◽

Tarun Kanti Bhattacharyya

Keyword(s):

High Speed ◽

Charge Pump ◽

Phase Frequency Detector ◽

Fast Acquisition ◽

Charge Pump Pll ◽

Low Jitter ◽

Frequency Detector

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A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2014.2327291 ◽

2014 ◽

Vol 61 (11) ◽

pp. 3278-3287 ◽

Cited By ~ 9

Author(s):

Fan-Ta Chen ◽

Min-Sheng Kao ◽

Yu-Hao Hsu ◽

Jen-Ming Wu ◽

Ching-Te Chiu ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Frequency Detector ◽

Single Loop ◽

Low Jitter ◽

Frequency Detector ◽

Rotational Phase

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A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) ◽

10.1109/mmica.1999.833606 ◽

2003 ◽

Author(s):

H. Wang ◽

R. Nottenburg

Keyword(s):

Clock Recovery ◽

Phase Frequency Detector ◽

Low Jitter ◽

Frequency Detector

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Effect of Scaling on Phase Frequency Detector

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.7.1.8280 ◽

2016 ◽

Vol 7 (1) ◽

pp. 20

Author(s):

GULIHAR LATIKA ◽

KRISHAN BAL ◽

◽

Keyword(s):

Phase Frequency Detector ◽

Frequency Detector

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МАКРОМОДЕЛИРОВАНИЕ СХЕМЫ ФАПЧ С ИСПОЛЬЗОВАНИЕМ ПОЛНОЙ ПРИНЦИПИАЛЬНОЙ СХЕМЫ ФАЗОВОГО ДЕТЕКТОРА

Nanoindustry Russia ◽

10.22184/1993-8578.2020.13.3s.295.299 ◽

2020 ◽

Vol 96 (3s) ◽

pp. 295-299

Author(s):

М.М. Гурарий ◽

М.М. Жаров ◽

Л.П. Ионов ◽

И.И. Мухин ◽

С.Г. Русаков ◽

...

Keyword(s):

Electric Circuit ◽

Schematic Diagram ◽

Equivalent Electric Circuit ◽

Phase Frequency Detector ◽

Frequency Detector ◽

A Current

В работе рассмотрены проблемы анализа схем ФАПЧ с учетом наличия неидеальностей в схеме частотно-фазового детектора с токовым ключом. Для снижения затрат на моделирование предложено использовать эквивалентную электрическую схему, содержащую полную принципиальную схему ЧФД и схемные эквиваленты макромоделей остальных блоков ФАПЧ. The paper considers the problems of analyzing the PLL circuit taking into account the presence of nonidealities in the phase-frequency detector with a current key. To reduce the simulation efforts, it has been proposed to apply an equivalent electric circuit containing the complete schematic diagram of the PFD and circuit equivalents of the macromodels of other PLL blocks.

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