A Variable Bandwidth High Speed FIR Filter Design for RFID Reader Receiver

2006 ◽  
Author(s):  
Yuan Liu ◽  
Chenling Huang ◽  
Peijun Gao ◽  
Hao Min
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Rfid Reader ◽  
Variable Bandwidth ◽  
Fir Filter Design

scholarly journals High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

2020 ◽  
Vol 9 (3) ◽  
pp. 764-770
Keyword(s):  
Decision Tree ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Decision Tree Algorithm ◽  
Tree Algorithm ◽  
Constant Multiplication ◽  
Field Programmable ◽  
Fir Filter Design ◽  
Complex Multiplier

In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

2019 ◽  
Vol 8 (10) ◽  
pp. 4288-4296
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Simulation Tools ◽  
Booth Multiplier ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Reduced Complexity ◽  
Fir Filter Design

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm

2012 ◽  
Author(s):  
Uwe Meyer-Baese ◽  
Guillermo Botella ◽  
David E. T. Romero ◽  
Martin Kumm
Keyword(s):  
Genetic Algorithm ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Fir Filter Design

scholarly journals Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

2018 ◽  
Vol 7 (2.32) ◽  
pp. 243
Author(s):  
U Penchalaiah ◽  
Siva Kumar VG
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Large Area ◽  
Processing Application ◽  
Carry Select Adder ◽  
Fir Filter Design

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

High Speed FIR Filter Using Radix-2r Multiplier and Its Application for Denoising EOG Signal

2021 ◽  
pp. 2150237
Author(s):  
Gundugonti Kishore Kumar ◽  
Balaji Narayanam
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Fir Filter ◽  
Path Delay ◽  
Critical Path Delay ◽  
Filter Architecture ◽  
Constant Multiplication ◽  
Fir Filter Design

In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-[Formula: see text] arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with [Formula: see text] compressors. This proposed architecture is implemented by using Radix-[Formula: see text]-based multiplier and [Formula: see text] compressor architectures for achieving better improvement in the critical path delay. The Radix-[Formula: see text]-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

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