Topology Virtualization for Throughput Maximization on Many-Core Platforms

Sum Throughput Maximization for MIMO Wireless Powered Communication Networks with Discrete Signal Inputs

IEICE Transactions on Communications ◽

10.1587/transcom.2018ebp3075 ◽

2019 ◽

Vol E102.B (5) ◽

pp. 1037-1044

Author(s):

Feng KE ◽

Xiaoyu HUANG ◽

Weiliang ZENG ◽

Yuqin LIU

Keyword(s):

Communication Networks ◽

Throughput Maximization ◽

Discrete Signal

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Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1640 ◽

2017 ◽

Vol E100.A (8) ◽

pp. 1640-1649

Author(s):

Hyunjik SONG ◽

Kiyoung CHOI

Keyword(s):

Simulated Annealing ◽

Load Balancing ◽

Many Core

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Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.360 ◽

2014 ◽

Vol E97.C (4) ◽

pp. 360-368

Author(s):

Takashi MIYAMORI ◽

Hui XU ◽

Hiroyuki USUI ◽

Soichiro HOSODA ◽

Toru SANO ◽

...

Keyword(s):

Low Power ◽

Many Core

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On Synchronization and Evaluation Method of Chipped Many-Core Processor

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2010.01777 ◽

2010 ◽

Vol 33 (10) ◽

pp. 1777-1787 ◽

Cited By ~ 1

Author(s):

Wei-Zhi XU ◽

Feng-Long SONG ◽

Zhi-Yong LIU ◽

Dong-Rui FAN ◽

Lei YU ◽

...

Keyword(s):

Evaluation Method ◽

Many Core

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Using Write Mask to Support Hybrid Write-Back and Write-Through Cache Policy on Many-Core Architectures

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.01918 ◽

2009 ◽

Vol 31 (11) ◽

pp. 1918-1928 ◽

Cited By ~ 3

Author(s):

Wei LIN ◽

Xiao-Chun YE ◽

Feng-Long SONG ◽

Hao ZHANG

Keyword(s):

Many Core

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Throughput Maximization Under Quality of Service Constraints: Determination of Optimal Offered Load in Circuit-Switched (Wireless or Nonwireless) Communication Networks

10.21236/ada389277 ◽

2000 ◽

Author(s):

Jeffrey E. Wieselthier ◽

Gam D. Nguyen ◽

Anthony Ephremides

Keyword(s):

Quality Of Service ◽

Communication Networks ◽

Throughput Maximization ◽

Service Constraints

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Research on highly parallel embedded control system design and implementation method

Impact ◽

10.21820/23987073.2019.10.44 ◽

2019 ◽

Vol 2019 (10) ◽

pp. 44-46

Author(s):

Masato Edahiro ◽

Masaki Gondo

Keyword(s):

Computer Architecture ◽

Intelligent Systems ◽

Large Scale ◽

General Purpose ◽

Heterogeneous Structure ◽

Single Chip ◽

Powertrain Control ◽

Processing Power ◽

Hardware Description ◽

Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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MILC Code Performance on High End CPU and GPU Supercomputer Clusters

EPJ Web of Conferences ◽

10.1051/epjconf/201817502009 ◽

2018 ◽

Vol 175 ◽

pp. 02009

Author(s):

Carleton DeTar ◽

Steven Gottlieb ◽

Ruizi Li ◽

Doug Toussaint

Keyword(s):

Conjugate Gradient ◽

Memory Hierarchy ◽

Xeon Phi ◽

Intel Xeon Phi ◽

Code Performance ◽

Recent Developments ◽

Knights Landing ◽

Many Core ◽

Intel Xeon

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.

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