ASIC design of MIPS based RISC processor for high performance

2017 ◽  
Author(s):  
Agineti Ashok ◽  
V. Ravi
Keyword(s):  
High Performance ◽  
Asic Design ◽  
Risc Processor

The CMOS gate forest: an efficient and flexible high-performance ASIC design environment

10.1109/4.999 ◽  
1988 ◽  
Vol 23 (2) ◽  
pp. 387-399 ◽  
Author(s):  
M.A. Beunder ◽  
J.P. Kernhof ◽  
B. Hoefflinger
Keyword(s):  
High Performance ◽  
Design Environment ◽  
Asic Design

PA7200: a PA-RISC processor with integrated high performance MP bus interface

2002 ◽  
Author(s):  
G. Kurpanek ◽  
K. Chan ◽  
J. Zheng ◽  
E. DeLano ◽  
W. Bryg
Keyword(s):  
High Performance ◽  
Risc Processor

Hierarchical Timing Signoff in High Performance ASIC Design

2014 ◽  
Vol 60 (1) ◽  
pp. 1203-1207
Author(s):  
G. Li ◽  
H. Dai ◽  
Z. Shi ◽  
J. Niu ◽  
J. Li
Keyword(s):  
High Performance ◽  
Asic Design ◽  
Hierarchical Timing

scholarly journals Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

2019 ◽  
Vol 8 (6S2) ◽  
pp. 790-796
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Random Access ◽  
Instruction Set ◽  
Cache Memories ◽  
Design And Implementation ◽  
Pipelined Architecture ◽  
Risc Processor ◽  
High Speed Data

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

scholarly journals Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

2020 ◽  
Vol 9 (3) ◽  
pp. 3783-3789
Keyword(s):  
Video Processing ◽  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Risc Processor ◽  
Small Set ◽  
Reduced Instruction Set Computer ◽  
Definition Of ◽  
Instruction Format

The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture

scholarly journals Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

2015 ◽  
Vol 15 (1) ◽  
pp. 81-88 ◽  
Author(s):  
Bikash Poduel ◽  
Prasanna Kansakar ◽  
Sujit R. Chhetri ◽  
Shashidhar Ram Joshi
Keyword(s):  
High Performance ◽  
Control Unit ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Risc Processor ◽  
Data Memory ◽  
Memory Register ◽  
Reduced Instruction Set Computer ◽  
Instruction Memory ◽  
Harvard Architecture

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021  Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

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