A Compression Layer for NAND Type Flash Memory Systems

2005 ◽  
Author(s):  
Wen-Tzeng Huang ◽  
Chun-Ta Chen ◽  
Yen-Sheng Chen ◽  
Chin-Hsing Chen
Keyword(s):  
Flash Memory ◽  
Memory Systems ◽  
Compression Layer

scholarly journals A Block Classification Method with Monitor and Restriction in NAND Flash memory

2021 ◽  
Vol 12 (5) ◽  
pp. 209-215
Author(s):  
Myungsub Lee
Keyword(s):  
Performance Evaluation ◽  
Standard Deviation ◽  
Flash Memory ◽  
Garbage Collection ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Wear Leveling ◽  
Block Classification ◽  
Update Frequency

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.

The Real-Time Compression Layer for Flash Memory in Mobile Multimedia Devices

2008 ◽  
Vol 13 (6) ◽  
pp. 547-554 ◽  
Author(s):  
Chin-Hsing Chen ◽  
Chun-Ta Chen ◽  
Wen-Tzeng Huang
Keyword(s):  
Real Time ◽  
Flash Memory ◽  
Mobile Multimedia ◽  
The Real ◽  
Time Compression ◽  
Compression Layer

scholarly journals Estimation of Ge nanocrystals size by Raman, X-rays, and HRTEM techniques

2008 ◽  
Vol 14 (S3) ◽  
pp. 61-64 ◽  
Author(s):  
S.R.C. Pinto ◽  
P. Caldelas ◽  
A.G. Rolo ◽  
A. Chahboun ◽  
M.J.M. Gomes
Keyword(s):  
Flash Memory ◽  
Nonvolatile Memory ◽  
High Dielectric Constant ◽  
Memory Systems ◽  
X Rays ◽  
Processing Conditions ◽  
Flash Memories ◽  
Potential Applications ◽  
High Dielectric ◽  
Ge Nanocrystals

Ge NCs have attracted considerable attention because of their potential applications in nonvolatile memory and integrated optoelectronics. A number of groups have already proposed integrate flash memories based on Ge NCs embedded SiO2 matrix. Since Al2O3 presents a high dielectric constant comparatively to SiO2, it is a good candidate to replace silica in flash memory systems, and therefore improve their performances. Moreover, Al2O3 presents good mechanical properties, and supports high temperature, which leads it to be an ideal material for Si processing conditions. However, a few studies have been reported on Ge NCs embedded in Al2O3 matrix.

Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems

2014 ◽  
Author(s):  
Nikolaos Papandreou ◽  
Thomas Parnell ◽  
Haralampos Pozidis ◽  
Thomas Mittelholzer ◽  
Evangelos Eleftheriou ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

scholarly journals A Study on Efficient FTL Algorithms for Flash Memory Systems

IJARCCE ◽  
2016 ◽  
Vol 5 (12) ◽  
pp. 144-146
Author(s):  
Sunil Kim ◽  
Jun-Yong Lee
Keyword(s):  
Flash Memory ◽  
Memory Systems

scholarly journals A Relative Reference Responsive LRU based Page Replacement Algorithm for NAND Flash Memory

Webology ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 62-76
Author(s):  
Hitha Paulson ◽  
Dr.R. Rajesh
Keyword(s):  
Flash Memory ◽  
Memory Systems ◽  
Management Technique ◽  
Hard Disks ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Replacement Algorithm ◽  
Replacement Procedure ◽  
Replacement Algorithms ◽  
Fast Access

The acceptance of NAND flash memories in the electronic world, due to its non-volatility, high density, low power consumption, small size and fast access speed is hopeful. Due to the limitations in life span and wear levelling, this memory needs special attention in its management techniques compared to the conventional techniques used in hard disks. In this paper, an efficient page replacement algorithm is proposed for NAND flash based memory systems. The proposed algorithm focuses on decision making policies based on the relative reference ratio of pages in memory. The size adjustable eviction window and the relative reference based shadow list management technique proposed by the algorithm contribute much to the efficiency in page replacement procedure. The simulation tool based experiments conducted shows that the proposed algorithm performs superior to the well-known flash based page replacement algorithms with regard to page hit ratio and memory read/write operations.

scholarly journals A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 365 ◽  
Author(s):  
Arul Subbiah ◽  
Tokunbo Ogunfunmi
Keyword(s):  
Finite Fields ◽  
Flash Memory ◽  
Search Algorithm ◽  
Memory Systems ◽  
Block Codes ◽  
General Purpose ◽  
Bch Codes ◽  
Nand Flash ◽  
Graphical Processing Units ◽  
Graphical Processing

Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2 m )). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput.

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