Study on first generation super flash memory cell fabrication using liftoff-techniques and its performance in floating gate and gate oxide thickness scaling

2017 ◽  
Author(s):  
Muhammad Amin Sulthoni ◽  
Bima Sahbani ◽  
Hasbi Ash Shiddieqy ◽  
Lindawani Siregar
Keyword(s):  
Flash Memory ◽  
First Generation ◽  
Memory Cell ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Floating Gate ◽  
Gate Oxide Thickness ◽  
Cell Fabrication ◽  
Flash Memory Cell

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

A new floating gate compact model applied to flash memory cell

2003 ◽  
Vol 322 (1-3) ◽  
pp. 250-255 ◽  
Author(s):  
R. Laffont ◽  
P. Masson ◽  
S. Bernardini ◽  
R. Bouchakour ◽  
J.M. Mirabel
Keyword(s):  
Flash Memory ◽  
Memory Cell ◽  
Floating Gate ◽  
Compact Model ◽  
Flash Memory Cell

In-Line Monitor Introduction to Prevent Metallic Contamination in Wet Bench

2005 ◽  
Vol 108-109 ◽  
pp. 637-642 ◽  
Author(s):  
Domenico Mello ◽  
Francesco Cordiano ◽  
Andrea Gerosa ◽  
Margherita Padalino ◽  
Carmelo Gagliano ◽  
...  
Keyword(s):  
Flash Memory ◽  
Production Line ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Contamination Level ◽  
Process Flow ◽  
Gate Oxide Thickness ◽  
Metallic Contaminants ◽  
The Impact ◽  
Metallic Contamination

Contamination controls are very important issues in microelectronics. Any wrong substance introduction in process chambers can cause damages to the production line. Therefore, an extensive control is important because every operation in the process flow (also the most insignificant) can become fatal for the correct functioning of a microelectronic device. The aim of this work is to evaluate the impact of small metallic contamination in the range of 1011÷1012 at/cm2 on silicon substrates implanted with different ion species (As, B and P). An important example of failure related to metallic contamination in a wet bench is reported in this work. The problem appears in a particular class of flash memory devices processing. The electrical parametric test shows a wrong gate oxide thickness and Qbd values out of range, confirmed by early breakdown events and anomalous C-V characteristics. The cause of the failure is morphologically identified off-line by using TEM: the cross section shows a wrong gate oxide thickness and an anomalous interface between gate oxide and silicon substrate. It appears clear that the root failure cause is related to the ion implantation (As in this case) and to the cleaning before gate oxide growth. A short process flow was performed and analyzed step by step in order to identify the failure cause. Many different analytical techniques have been used for each step and all of these provide consistent results. In particular TXRF analysis on wafers processed immediately after cleaning do not show any contamination while Cu and Fe contaminants are observed after sample oxidation and As implant. Metallic contaminants are captured by the substrate after it is implanted with As, and the following RCA cleaning is not able to remove them. In addition, the presence of these metallic contaminants induces roughness of the Si surface and the growth of gate oxide is not controlled (faster oxidation). If different substrates are used, e.g. silicon implanted with B or un-implanted, this contamination level is not detected and does not lead to oxide reliability problems. Once the mechanism of metal contaminant interaction with dopant is identified the introduction of an in-line monitoring is possible, thus allowing to prevent the device failure. The short process loop can be considered as a good method to prepare the substrate before TXRF analysis. After this study the monitor has been integrated in the production line controls

High Speed, Low Power Programming in 0.17µm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects

2004 ◽  
Vol 43 (No. 2A) ◽  
pp. L224-L226
Author(s):  
Chang-Ki Baek ◽  
Yunheub Song ◽  
Bomsoo Kim ◽  
Wu-yun Quan ◽  
Young June Park ◽  
...  
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Speed ◽  
Memory Cell ◽  
Channel Length ◽  
Floating Gate ◽  
Turn On ◽  
Flash Memory Cell
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