High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine

2006 ◽  
Author(s):  
Yusuke Yachide ◽  
Makoto Ikeda ◽  
Kunihiro Asada
Keyword(s):  
Measurement System ◽  
High Speed ◽  
Image Sensor

scholarly journals A Research and Application of the Processing Methods of Railway Measurement Based on Self-Mobile Scanning Measurement System

2020 ◽  
Author(s):  
Jiancai Zhang ◽  
Hang Mu ◽  
Feng Han ◽  
Shumin Han
Keyword(s):  
Measurement System ◽  
High Speed ◽  
Automatic Segmentation ◽  
Laser Scanner ◽  
Region Growing ◽  
Image Sensor ◽  
Operating Conditions ◽  
Secondary Development ◽  
Railway Line ◽  
Region Growing Segmentation

With the gradual improvement of China’s railway net, the opening of international railways as well as the continuous growth of railway operating mileage, the workload of remeasuring railways is increasing. The traditional methods of remeasuring railways can not meet current high-speed and high-density operating conditions anymore in terms of safety, efficiency and quality, so a safer and more efficient measurement method is urgently needed.This thesis integrated various sensors on a self-mobile instrument, such as 3D laser scanner, digital image sensor and GNSS_IMU, designing a set of intelligent and integrated self-mobile scanning measurement system. This thesis proposed region growing segmentation based on the reflection intensity of point cloud. Through the secondary development of CAD, the menu for automatic processing of self-mobile scanning measurement system is designed to realize rail automatic segmentation, extraction of rail top points, fitting of plane parameters of railway line, calculation of curve elements and mileage management.The results show that self-mobile scanning measurement system overcomes the shortcomings of traditional railway measurement to some extent, and realizes intelligent measurement of railways.

Design and implementation of high-speed multiwavelength pyrometry measurement system based on CMOS image sensor

2011 ◽  
Vol 9 (s1) ◽  
pp. s10304-310306
Author(s):  
Bo Wang Bo Wang ◽  
Yonglin Bai Yonglin Bai ◽  
Baiyu Liu Baiyu Liu ◽  
Xiaohong Bai Xiaohong Bai ◽  
Wenzheng Yang Wenzheng Yang ◽  
...  
Keyword(s):  
Measurement System ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Design And Implementation ◽  
Multiwavelength Pyrometry

scholarly journals Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 1955
Author(s):  
Md Jubaer Hossain Pantho ◽  
Pankaj Bhowmik ◽  
Christophe Bobda
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Image Sensor ◽  
Machine Learning Algorithms ◽  
Hierarchical Optimization ◽  
Computation Method ◽  
Optimization Approach ◽  
Efficient Computation ◽  
Feature Maps ◽  
Dynamic Power

The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

scholarly journals On-CMOS Image Sensor Processing for Lane Detection

Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3713
Author(s):  
Soyeon Lee ◽  
Bohyeok Jeong ◽  
Keunyeol Park ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Edge Detection ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Image Resolution ◽  
Lane Detection ◽  
Frame Rate ◽  
Total Power ◽  
Detection Accuracy ◽  
Total Power Consumption

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

High-speed CMOS image sensor circuits with in situ frame storage

2004 ◽  
Vol 51 (4) ◽  
pp. 1648-1656 ◽  
Author(s):  
S. Kleinfelder ◽  
Yandong Chen ◽  
K. Kwiatkowski ◽  
A. Shah
Keyword(s):  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor

Development of high speed measurement system for cell-scaffold interaction

2015 ◽  
Author(s):  
Yu Hirano ◽  
Masaru Kojima ◽  
Mitsuhiro Horade ◽  
Kazuto Kamiyama ◽  
Yasushi Mae ◽  
...  
Keyword(s):  
Measurement System ◽  
High Speed ◽  
Speed Measurement ◽  
Cell Scaffold

High speed automated pulsed I/V measurement system

1993 ◽  
Author(s):  
T. Fernandez ◽  
Y. Newport ◽  
J.M. Zamanillo ◽  
A. Mediavilla ◽  
A. Tazon
Keyword(s):  
Measurement System ◽  
High Speed
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