Low Power Instruction Cache with Word Selective Line Buffer

2012 ◽  
Author(s):  
Hyun-Bum Cho ◽  
Ju-Hee Choi ◽  
Seong-Tea Jhang ◽  
Chu-Shik Jhon
Keyword(s):  
Low Power ◽  
Instruction Cache

Low power instruction cache design based on branch execution tracks

2013 ◽  
Author(s):  
Quanquan Li ◽  
Qi Wang ◽  
Tiejun Zhang ◽  
Donghui Wang ◽  
Chaohuan Hou
Keyword(s):  
Low Power ◽  
Instruction Cache ◽  
Cache Design

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

2013 ◽  
Vol 4 (2) ◽  
pp. 50-61
Author(s):  
Yul Chu ◽  
Marven Calagos
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Access Time ◽  
Data Cache ◽  
Instruction Cache ◽  
Prediction Mode ◽  
Access Mode ◽  
Cache Scheme ◽  
Better Than

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache

2009 ◽  
Vol E92-C (4) ◽  
pp. 517-521
Author(s):  
Gi-Ho PARK ◽  
Jung-Wook PARK ◽  
Hoi-Jin LEE ◽  
Gunok JUNG ◽  
Sung-Bae PARK ◽  
...  
Keyword(s):  
Low Power ◽  
Branch Prediction ◽  
Instruction Cache
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