A compiler-controlled instruction cache architecture for an embedded low power microprocessor

2005 ◽  
Author(s):  
Xiaoping Zhu ◽  
T.T. Tay
Keyword(s):  
Low Power ◽  
Instruction Cache ◽  
Cache Architecture

Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags

2019 ◽  
Vol 28 (12) ◽  
pp. 1950203
Author(s):  
Sajjad Rostami-Sani ◽  
Mojtaba Valinataj ◽  
Saeideh Alinezhad Chamazcoti
Keyword(s):  
Energy Consumption ◽  
System Performance ◽  
Bloom Filter ◽  
Instruction Cache ◽  
Cache Architecture ◽  
Power Set ◽  
Novel Method ◽  
Instruction Caches ◽  
Cache System ◽  
Counting Bloom Filter

The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16[Formula: see text]kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system.

A low-power phase change memory based hybrid cache architecture

2008 ◽  
Author(s):  
Prasanth Mangalagiri ◽  
Karthik Sarpatwari ◽  
Aditya Yanamandra ◽  
VijayKrishnan Narayanan ◽  
Yuan Xie ◽  
...  
Keyword(s):  
Low Power ◽  
Phase Change ◽  
Phase Change Memory ◽  
Cache Architecture ◽  
Hybrid Cache ◽  
Change Memory

Low power instruction cache design based on branch execution tracks

2013 ◽  
Author(s):  
Quanquan Li ◽  
Qi Wang ◽  
Tiejun Zhang ◽  
Donghui Wang ◽  
Chaohuan Hou
Keyword(s):  
Low Power ◽  
Instruction Cache ◽  
Cache Design
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