CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash

2017 ◽  
Author(s):  
Meng Zhang ◽  
Fei Wu ◽  
Yajuan Du ◽  
Chengmo Yang ◽  
Changsheng Xie ◽  
...  
Keyword(s):  
Error Correction ◽  
Nand Flash ◽  
Ldpc Decoding ◽  
Correction Scheme

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

2022 ◽  
Vol 27 (1) ◽  
pp. 1-20
Author(s):  
Lanlan Cui ◽  
Fei Wu ◽  
Xiaojian Liu ◽  
Meng Zhang ◽  
Renzhi Xiao ◽  
...  
Keyword(s):  
Error Correction ◽  
Distribution Model ◽  
Quantization Scheme ◽  
Nand Flash ◽  
Soft Decision ◽  
Ldpc Decoding ◽  
Error Correction Capability ◽  
Soft Decision Decoding ◽  
Threshold Voltage Distribution ◽  
Hard Decision

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems

2016 ◽  
Vol E99.C (2) ◽  
pp. 293-301 ◽  
Author(s):  
Youngjoo LEE ◽  
Jaehwan JUNG ◽  
In-Cheol PARK
Keyword(s):  
Storage Systems ◽  
Nand Flash ◽  
Ldpc Decoding

Realization of NAND FLASH Control Glueless Interface Circuit

2014 ◽  
Vol 1008-1009 ◽  
pp. 659-662
Author(s):  
Hai Ke Liu ◽  
Shun Wang ◽  
Xin Gna Kang ◽  
Jin Liang Wang
Keyword(s):  
Error Correction ◽  
Code Generation ◽  
Nand Flash ◽  
Timing Control ◽  
Interface Circuit ◽  
Advantages And Disadvantages ◽  
Operation Sequence ◽  
Control Interface

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory

2019 ◽  
Vol 38 (12) ◽  
pp. 2312-2320 ◽  
Author(s):  
Meng Zhang ◽  
Fei Wu ◽  
Yajuan Du ◽  
Weihua Liu ◽  
Changsheng Xie
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Ldpc Decoding

scholarly journals Efficient error correcting scheme for chaos shift keying signals

2019 ◽  
Vol 9 (5) ◽  
pp. 3550
Author(s):  
Hikmat N. Abdullah ◽  
Thamir R. Saeed ◽  
Asaad H. Sahar
Keyword(s):  
Error Correction ◽  
Logistic Map ◽  
Chaotic Sequence ◽  
Chaos Communication ◽  
Shortest Distance ◽  
Correction Scheme ◽  
Shift Keying ◽  
Minimum Delay ◽  
Modified Logistic Map ◽  
Chaos Shift Keying

An effective error-correction scheme based on normalized correlation for a non coherent chaos communication system with no redundancy bits is proposed in this paper. A modified logistic map is used in the proposed scheme for generating two sequences, one for every data bit value, in a manner that the initial value of the next chaotic sequence is set by the second value of the present chaotic sequence of the similar symbol. This arrangement, thus, has the creation of successive chaotic sequences with identical chaotic dynamics for error correction purpose. The detection symbol is performed prior to correction, on the basis of the suboptimal receiver which anchors on the computation of the shortest distance existing between the received sequence and the modified logistic map’s chaotic trajectory. The results of the simulation reveal noticeable Eb/No improvement by the proposed scheme over the prior to the error- correcting scheme with the improvement increasing whenever there is increase in the number of sequence N. Prior to the error-correcting scheme when N=8, a gain of 1.3 dB is accomplished in E<sub>b</sub>/N<sub>o</sub> at 10<sup>-3 </sup>bit error probability. On the basis of normalized correlation, the most efficient point in our proposed error correction scheme is the absence of any redundant bits needed with minimum delay procedure, in contrast to earlier method that was based on suboptimal method detection and correction. Such performance would render the scheme good candidate for applications requiring high rates of data transmission.

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