scholarly journals Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

2011 ◽  
Author(s):  
Pramod Subramanyan ◽  
Virendra Singh ◽  
Kewal K. Saluja ◽  
Erik Larsson
Keyword(s):  
Chip Multiprocessors ◽  
Fault Tolerant ◽  
Adaptive Execution

Design of a Reliable Cache System for Heterogeneous CMPs

2018 ◽  
Vol 27 (14) ◽  
pp. 1850219 ◽  
Author(s):  
Bidesh Chakraborty ◽  
Mamata Dalui ◽  
Biplab K. Sikdar
Keyword(s):  
Embedded System ◽  
Chip Multiprocessors ◽  
Fault Tolerant ◽  
Data Block ◽  
Heterogeneous Processors ◽  
Von Neumann ◽  
High Scalability ◽  
The Embedded System ◽  
Efficient Verification ◽  
Cache System

The embedded system-on-a-chip (SoC), that integrates heterogeneous processors with variation in coherence protocol, adds complexity in maintaining coherency in the data caches. It further complicates the task of coherence verification in such systems. This work targets effective solution for coherence verification in heterogeneous chip multiprocessors (CMPs) through introduction of highly efficient verification unit. It is developed around the modeling tool of cellular automaton (CA) invented by von Neumann in 1950s. The modular and cascadable structure of CA ensures high scalability and robustness in the proposed design. A CA segment is employed to analyze the states of a data block in different private caches of a heterogeneous processor cluster and to verify inconsistencies, if any, within the cluster. The outcomes of coherence verification for clusters are analyzed by the CA resulted out of augmentation of the CA segments. On the other hand, in this work, we further propose a CA-based coherence protocol processor (PP), which caters the need for determining the state of a data block with high accuracy. The PP designed for the heterogeneous CMPs, while computing the states of za block on every transaction (read/write), can capture defects, if any, and thereby realizes a fault-tolerant PP without introduction of additional hardware logic.

NoC-based fault-tolerant cache design in chip multiprocessors

2014 ◽  
Vol 13 (3s) ◽  
pp. 1-26 ◽  
Author(s):  
Abbas Banaiyanmofrad ◽  
Gustavo Girão ◽  
Nikil Dutt
Keyword(s):  
Chip Multiprocessors ◽  
Fault Tolerant ◽  
Cache Design
Sign in / Sign up

Export Citation Format

Share Document