Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240952 ◽

2004 ◽

Cited By ~ 54

Author(s):

M. Dall'Osso ◽

G. Biccari ◽

L. Giovannini ◽

D. Bertozzi ◽

L. Benini

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466126 ◽

2005 ◽

Cited By ~ 2

Author(s):

Liang-Yu Lin ◽

Cheng-Yeh Wang ◽

Pao-Jui Huang ◽

Chih-Chieh Chou ◽

Jing-Yang Jou

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs

2012 IEEE 30th International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2012.6378615 ◽

2012 ◽

Cited By ~ 8

Author(s):

Matteo Dall'Osso ◽

Gianluca Biccari ◽

Luca Giovannini ◽

Davide Bertozzi ◽

Luca Benini

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05 ◽

10.1145/1120725.1120739 ◽

2005 ◽

Cited By ~ 12

Author(s):

Liang-Yu Lin ◽

Cheng-Yeh Wang ◽

Pao-Jui Huang ◽

Chih-Chieh Chou ◽

Jing-Yang Jou

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

On Chip

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.5.1.3320 ◽

2014 ◽

Vol 5 (1) ◽

pp. 27-32

Author(s):

Jeeva Anusha ◽

◽

V. Thrimurthulu ◽

Keyword(s):

Vlsi Design ◽

Network On Chip ◽

Energy Modeling ◽

Low Energy ◽

On Chip

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Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2012.00654 ◽

2014 ◽

Vol 35 (2) ◽

pp. 341-346

Author(s):

Xiao-fu Zheng ◽

Hua-xi Gu ◽

Yin-tang Yang ◽

Zhong-fan Huang

Keyword(s):

Network On Chip ◽

Low Latency ◽

Router Architecture ◽

On Chip

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Example Antenna and Link Performance for Wireless Network on Chip Applications

12th European Conference on Antennas and Propagation (EuCAP 2018) ◽

10.1049/cp.2018.0956 ◽

2018 ◽

Author(s):

W. Rayess ◽

D.W. Matolak

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Link Performance ◽

On Chip

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An optimized path-setup method for mesh based Optical Network on Chip

2015 14th International Conference on Optical Communications and Networks (ICOCN) ◽

10.1109/icocn.2015.7203619 ◽

2015 ◽

Author(s):

Wei Tan ◽

Bowen Zhang ◽

Huaxi Gu ◽

Zheng Chen

Keyword(s):

Optical Network ◽

Network On Chip ◽

On Chip

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A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9332940 ◽

2020 ◽

Author(s):

Jiayi Liu ◽

Kejie Huang

Keyword(s):

Network On Chip ◽

Convolutional Networks ◽

On Chip

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