A Compact model for analysis and design of on-chip power network with decoupling capacitors

2004 ◽  
Author(s):  
P. Zarkesh-Ha ◽  
K. Doniger ◽  
W. Loh ◽  
D. Sun ◽  
R. Stephani ◽  
...  
Keyword(s):  
Compact Model ◽  
Power Network ◽  
Decoupling Capacitors ◽  
Analysis And Design ◽  
On Chip

Analysis and Design of On-Chip Decoupling Capacitors

2013 ◽  
Vol 21 (4) ◽  
pp. 648-658 ◽  
Author(s):  
Tasreen Charania ◽  
Ajoy Opal ◽  
Manoj Sachdev
Keyword(s):  
Decoupling Capacitors ◽  
Analysis And Design ◽  
On Chip

Design of R3TOS based reliable low power network on chip

2017 ◽  
Author(s):  
N Poornima ◽  
Seetharaman Gopalakrishnan ◽  
Tughrul Arsalan ◽  
T. N. Prabakar ◽  
M. Santhi
Keyword(s):  
Low Power ◽  
Network On Chip ◽  
Power Network ◽  
On Chip

Noise Characteristics of On-Chip Power Networks with Decoupling Capacitors

2016 ◽  
pp. 491-500
Author(s):  
Inna P.-Vaisband ◽  
Renatas Jakushokas ◽  
Mikhail Popovich ◽  
Andrey V. Mezhiba ◽  
Selçuk Köse ◽  
...  
Keyword(s):  
Power Networks ◽  
Decoupling Capacitors ◽  
Noise Characteristics ◽  
On Chip

Power Distribution Networks with On-Chip Decoupling Capacitors

2011 ◽  
Author(s):  
Renatas Jakushokas ◽  
Mikhail Popovich ◽  
Andrey V. Mezhiba ◽  
Selçuk Köse ◽  
Eby G. Friedman
Keyword(s):  
Power Distribution ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Decoupling Capacitors ◽  
On Chip

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

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