Field-programmable integrated circuits-overview and future trends

2003 ◽  
Author(s):  
A. El Gamal
Keyword(s):  
Integrated Circuits ◽  
Future Trends ◽  
Field Programmable

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

2014 ◽  
pp. 347-371 ◽  
Author(s):  
Naim Harb ◽  
Smail Niar ◽  
Mazen A. R. Saghir
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Transportation Systems ◽  
Base System ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Mtt Algorithm

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

The Impact of Carbon Nanotubes and Graphene on Electronics Industry

2018 ◽  
pp. 2897-2907
Author(s):  
Rafael Vargas-Bernal ◽  
Gabriel Herrera-Pérez ◽  
Margarita Tecpoyotl-Torres
Keyword(s):  
Carbon Nanotubes ◽  
Electrical Properties ◽  
Integrated Circuits ◽  
Electronics Industry ◽  
Future Trends ◽  
Technology Roadmap ◽  
The World ◽  
Materials Used ◽  
Short Time ◽  
The Impact

Since its discovery in 1991 and 2004, carbon nanotubes (CNTs) by Sumio Iijima, and graphene by Andre Geim and Konstantin Novoselov in 2004, these materials have been extensively studied around the world. Both materials have electronic, thermal, magnetic, optical, chemical, and mechanical extraordinary properties. International Technology Roadmap for Semiconductors (ITRS) has predicted that these nanomaterials are potential replacements of the conventional materials used in the manufacture of integrated circuits. Two of the technological aspects that both materials share and have reduced their extensive use are processing and dispersion required to homogenize the electrical properties of the materials based on them. Fortunately, these problems are being solved thanks to the ongoing investigation, and in a short time the materials used in today's electronics industry will be replaced by devices based on these novel materials. The impact of the applications of both materials in the electronics industry, as well as future trends in the following decades are discussed in this paper.

EVOLVING DECISION TREES IN HARDWARE

2009 ◽  
Vol 18 (06) ◽  
pp. 1033-1060 ◽  
Author(s):  
RASTISLAV J. R. STRUHARIK ◽  
LADISLAV A. NOVAK
Keyword(s):  
Integrated Circuits ◽  
Decision Tree ◽  
Decision Trees ◽  
Adaptive Learning ◽  
Software Evolution ◽  
Fpga Implementation ◽  
Software Implementation ◽  
Navigation Systems ◽  
Field Programmable ◽  
Tree Inference

This paper, according to the best of our knowledge, provides the very first solution to the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by a significant improvement in the evolution time compared to the time needed for software evolution and efficient use of decision trees in various embedded applications (robotic navigation systems, image processing systems, etc.), where run-time adaptive learning is of particular interest. Several architectures for the hardware evolution of single oblique or nonlinear decision trees and ensembles comprised from oblique or nonlinear decision trees are presented. Proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Results of experiments obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in inference time when compared with the traditional software implementations. In the case of single decision tree evolution, FPGA implementation of H_DTS2 architecture has on average 26 times shorter inference time when compared to the software implementation, whereas FPGA implementation of H_DTE2 architecture has on average 693 times shorter inference time than the software implementation.

A Prototyping Environment for Hardware/Software Codesign of OFDM Systems

2013 ◽  
Vol 380-384 ◽  
pp. 2803-2806
Author(s):  
Xu Ming Lu ◽  
Wei Jie Wen ◽  
Hong Zhou Tan
Keyword(s):  
Integrated Circuits ◽  
Data Transmission ◽  
Hardware Implementation ◽  
Ofdm Systems ◽  
Ofdm System ◽  
Field Programmable ◽  
Software And Hardware ◽  
Front End Module ◽  
Application Specific ◽  
Insight Into

To make rapid implementation and verification for the systems becomes important in frontend Application Specific Integrated Circuits. Therefore, a field programmable gate array based hardware/software codesign prototyping environment is proposed to simulate the software implementation and verify the hardware implementation of a baseband OFDM system. The system is implemented by software and hardware partitions, respectively. The analog radio frequency front-end module helps take a full insight into the actual baseband system performance. User datagram protocol is used for data transmission between these two partitions, and hence makes a complete baseband system. With the proposed codesign environment, the software simulation is running over real wireless channels, and the hardware implemental results can be flexibly processed in real time and enhances the design efficiency.

scholarly journals FPGA Realization of Deep Neural Network for Hardware Trojan Detection

2020 ◽  
Vol 9 (3) ◽  
pp. 764
Author(s):  
Varun Reddy ◽  
Nirmala Devi M
Keyword(s):  
Neural Network ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Deep Neural Network ◽  
Random Forest Classifier ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Field Programmable

With the increase in outsourcing design and fabrication, malicious third-party vendors often insert hardware Trojan (HT) in the integrated Circuits(IC). It is difficult to identify these Trojans since the nature and characteristics of each Trojan differ significantly. Any method developed for HT detection is limited by its capacity on dealing with varied types of Trojans. The main purpose of this study is to show using deep learning (DL), this problem can be dealt with some extent and the effect of deep neural network (DNN) when it is realized on field programmable gate array (FPGA). In this paper, we propose a comparison of accuracy in finding faults on ISCAS’85 benchmark circuits between random forest classifier and DNN. Further for the faster processing time and less power consumption, the network is implemented on FPGA. The results show the performance of deep neural network gets better when a large number of nets are used and faster in the execution of the algorithm. Also, the speedup of the neuron is 100x times better when implemented on FPGA with 15.32% of resource utilization and provides less power consumption than GPU.

scholarly journals High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications

2020 ◽  
Vol 17 (3) ◽  
pp. 79-88
Author(s):  
Maarten Cauwe ◽  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Marnix Van De Slyeke ◽  
Erwin Bosman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Boards ◽  
Digital Signal ◽  
High Density ◽  
Circuit Boards ◽  
Space Applications ◽  
Track Width ◽  
Printed Circuit ◽  
Field Programmable ◽  
Space Projects

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

scholarly journals Searching for metastable particles using graph computing

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Ashutosh V. Kotwal
Keyword(s):  
Integrated Circuits ◽  
Hadron Collider ◽  
Decay Products ◽  
Pixel Sensors ◽  
Array Technology ◽  
Experimental Apparatus ◽  
Field Programmable ◽  
Computing Platforms ◽  
Graph Computing ◽  
Silicon Based

AbstractThe reconstruction of charged particle trajectories at the Large Hadron Collider and future colliders relies on energy depositions in sensors placed at distances ranging from a centimeter to a meter from the colliding beams. We propose a method of detecting charged particles that decay invisibly after traversing a short distance of about 25 cm inside the experimental apparatus. One of the decay products may constitute the dark matter known to be 84% of all matter at galactic and cosmological distance scales. Our method uses graph computing to cluster spacepoints recorded by two-dimensional silicon pixel sensors into mathematically-defined patterns. The algorithm may be implemented on silicon-based integrated circuits using field-programmable gate array technology to augment or replace traditional computing platforms.

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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