Analysis of various adder circuits in deep submicron process

2016 ◽  
Author(s):  
Sayli S. Aphale ◽  
Kausar Fakir ◽  
Sushama Kodagali ◽  
S.S. Mande
Keyword(s):  
Deep Submicron ◽  
Submicron Process

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

2008 ◽  
Author(s):  
Vincent Goiffon ◽  
Pierre Magnan ◽  
Frédéric Bernard ◽  
Guy Rolland ◽  
Olivier Saint-Pé ◽  
...  
Keyword(s):  
Ionizing Radiation ◽  
Radiation Effects ◽  
Deep Submicron ◽  
Cmos Imagers ◽  
Submicron Process

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

2011 ◽  
Vol 58 (6) ◽  
pp. 2719-2725 ◽  
Author(s):  
N. N. Mahatme ◽  
S. Jagannathan ◽  
T. D. Loveless ◽  
L. W. Massengill ◽  
B. L. Bhuva ◽  
...  
Keyword(s):  
Deep Submicron ◽  
Error Rates ◽  
Submicron Process

Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes

2018 ◽  
Vol 27 (03n04) ◽  
pp. 1840018
Author(s):  
Mst Shamim Ara Shawkat ◽  
Mohammad Habib Ullah Habib ◽  
Md Sakib Hasan ◽  
Mohammad Aminul Haque ◽  
Nicole McFarlane
Keyword(s):  
Electric Field ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Gate Voltage ◽  
Electric Field Distribution ◽  
Device Simulation ◽  
Deep Submicron ◽  
Uniform Electric Field ◽  
Cmos Process ◽  
Submicron Process

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

A Digitally Controlled Oscillator for ADPLL Application

2012 ◽  
Vol 229-231 ◽  
pp. 1515-1518
Author(s):  
Xiu Long Wu ◽  
Fa Niu Wang ◽  
Zhi Ting Lin ◽  
Jun Ning Chen
Keyword(s):  
Deep Submicron ◽  
Output Frequency ◽  
Sigma Delta ◽  
Digital Rf ◽  
Submicron Process ◽  
Digitally Controlled ◽  
Lc Oscillators ◽  
New Type ◽  
Digitally Controlled Oscillator ◽  
Mos Varactor

In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication. This new type of oscillator uses MOS varactor arrays to moderating the output frequency, through the using of digitally Sigma-Delta technology, we can get more precise resolution , and through using three modes progressively working way can make this kind of structure easily implement in process.

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