Memory Efficient, High Speed Implementation of MAX LOG MAP Decoder for CCSDS Turbo codes

2013 ◽  
Author(s):  
Bibin Varghese ◽  
V.K. Ansha ◽  
S. Sreelal ◽  
N. Shanu
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Map Decoder ◽  
Log Map ◽  
Memory Efficient

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

2006 ◽  
Vol 42 (16) ◽  
pp. 907 ◽  
Author(s):  
K. Mei ◽  
N. Zheng ◽  
H. van de Wetering
Keyword(s):  
High Speed ◽  
Vlsi Design ◽  
Memory Efficient

scholarly journals A Memory-Efficient and High-Speed Sine/Cosine Generator Based on Parallel CORDIC Rotations

2004 ◽  
Vol 11 (2) ◽  
pp. 152-155 ◽  
Author(s):  
S.-F. Hsiao ◽  
Y.-H. Hu ◽  
T.-B. Juang
Keyword(s):  
High Speed ◽  
Memory Efficient

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

A Memory-Efficient Block-wise MAP Decoder Architecture

ETRI Journal ◽  
2004 ◽  
Vol 26 (6) ◽  
pp. 615-621 ◽  
Author(s):  
Sik Kim ◽  
Sun-Young Hwang ◽  
Moon Jun Kang
Keyword(s):  
Decoder Architecture ◽  
Map Decoder ◽  
Memory Efficient
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