High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

2006 ◽  
Vol 42 (16) ◽  
pp. 907 ◽  
Author(s):  
K. Mei ◽  
N. Zheng ◽  
H. van de Wetering
Keyword(s):  
High Speed ◽  
Vlsi Design ◽  
Memory Efficient

VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000

Integration ◽  
2012 ◽  
Vol 45 (1) ◽  
pp. 1-8 ◽  
Author(s):  
Kishor Sarawadekar ◽  
Swapna Banerjee
Keyword(s):  
High Speed ◽  
Vlsi Design ◽  
Jpeg 2000 ◽  
Memory Efficient

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

2016 ◽  
Vol 5 (03) ◽  
pp. 07-12
Author(s):  
Prof. Amruta Bijwar
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Full Adder ◽  
Basic Component ◽  
Xnor Gate ◽  
Transmission Gates ◽  
Design Systems ◽  
Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

scholarly journals A Memory-Efficient and High-Speed Sine/Cosine Generator Based on Parallel CORDIC Rotations

2004 ◽  
Vol 11 (2) ◽  
pp. 152-155 ◽  
Author(s):  
S.-F. Hsiao ◽  
Y.-H. Hu ◽  
T.-B. Juang
Keyword(s):  
High Speed ◽  
Memory Efficient

BFAST: High-Speed and Memory-Efficient Approach for NDN Forwarding Engine

2017 ◽  
Vol 25 (2) ◽  
pp. 1235-1248 ◽  
Author(s):  
Huichen Dai ◽  
Jianyuan Lu ◽  
Yi Wang ◽  
Tian Pan ◽  
Bin Liu
Keyword(s):  
High Speed ◽  
Efficient Approach ◽  
Forwarding Engine ◽  
Memory Efficient
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