Silicon debug of a co-processor array for video applications

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889558 ◽

2002 ◽

Cited By ~ 9

Author(s):

B. Vermeulen ◽

G.J. van Rootselaar

Keyword(s):

Processor Array ◽

Silicon Debug

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DESIGNING A SYSTOLIC ALGORITHM FOR GENERATING WELL-FORMED PARENTHESIS STRINGS

Parallel Processing Letters ◽

10.1142/s0129626404001738 ◽

2004 ◽

Vol 14 (01) ◽

pp. 83-97

Author(s):

JONG-CHUANG TSAY

Keyword(s):

Linear Array ◽

Vlsi Implementation ◽

Processor Array ◽

Lexicographical Order ◽

Systolic Algorithm ◽

Left And Right ◽

Local Connection

A parenthesis string is a string of left and right parentheses. The string is well-formed when it consists of balanced pairs of left and right parentheses. This study presents a novel systolic algorithm for generating all the well-formed parenthesis strings in lexicographical order. The algorithm is cost-optimal and is run on a linear array of processors such that each well-formed parenthesis string can be generated in three time steps. The processor array is appropriate for VLSI implementation, since it has the features of modularity, regularity, and local connection.

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Analysis of replicated data algorithms on processor array architectures

Proceedings of the 1991 ACM/IEEE conference on Supercomputing - Supercomputing '91 ◽

10.1145/125826.126182 ◽

1991 ◽

Cited By ~ 2

Author(s):

P. J. Narayanan

Keyword(s):

Processor Array ◽

Replicated Data

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Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681431 ◽

2010 ◽

Cited By ~ 1

Author(s):

Kazuei Hironaka ◽

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

...

Keyword(s):

Power Consumption ◽

Reducing Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

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Trace Buffer Attack: Security versus observability study in post-silicon debug

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314443 ◽

2015 ◽

Cited By ~ 9

Author(s):

Yuanwen Huang ◽

Anupam Chattopadhyay ◽

Prabhat Mishra

Keyword(s):

Silicon Debug

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Design methodology for systematic derivation of fault-tolerant processor array architectures

International Journal of Electronics ◽

10.1080/002072198134463 ◽

1998 ◽

Vol 84 (6) ◽

pp. 615-624 ◽

Cited By ~ 1

Author(s):

D. SOUDRIS ◽

P. POECHMUELLER ◽

E. D. KYRIAKIS-BITZAROS ◽

M. BIRBAS ◽

C. GOUTIS ◽

...

Keyword(s):

Design Methodology ◽

Fault Tolerant ◽

Processor Array ◽

Systematic Derivation

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A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2011.2131370 ◽

2011 ◽

Vol 58 (10) ◽

pp. 2420-2431 ◽

Cited By ~ 54

Author(s):

Alexey Lopich ◽

Piotr Dudek

Keyword(s):

Processor Array ◽

Vision Chip ◽

Asynchronous Processing

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A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

Parallel Processing Letters ◽

10.1142/s0129626493000198 ◽

1993 ◽

Vol 03 (02) ◽

pp. 157-164 ◽

Cited By ~ 2

Author(s):

P. THANGAVEL ◽

V.P. MUTHUSWAMY

Keyword(s):

Parallel Algorithm ◽

Linear Array ◽

Constant Time ◽

Processor Array ◽

Gray Codes ◽

System A ◽

Processor Arrays ◽

Bus System

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

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