A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference ◽

10.1109/glocom.2007.620 ◽

2007 ◽

Cited By ~ 18

Author(s):

Massimo Rovini ◽

Giuseppe Gentile ◽

Francesco Rossi ◽

Luca Fanucci

Keyword(s):

Ldpc Codes ◽

Ieee 802.11N ◽

Decoder Architecture

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Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378835 ◽

2007 ◽

Cited By ~ 35

Author(s):

Kiran Gunnam ◽

Gwan Choi ◽

Weihuang Wang ◽

Mark Yeary

Keyword(s):

Ldpc Codes ◽

Ieee 802.11N ◽

Decoder Architecture

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2-dimensional minimum fast-searching design approach of LDPC decoder architecture for IEEE 802.11n/ac/ax applications

2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW) ◽

10.1109/icce-china.2017.7991024 ◽

2017 ◽

Author(s):

Xin-Yu Shih ◽

Yu-Chun Chen

Keyword(s):

Design Approach ◽

Ieee 802.11N ◽

Ldpc Decoder ◽

Decoder Architecture ◽

Fast Searching

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Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06 ◽

10.1145/1127908.1127980 ◽

2006 ◽

Cited By ~ 3

Author(s):

Yongmei Dai ◽

Zhiyuan Yan ◽

Ning Chen

Keyword(s):

Ldpc Codes ◽

Decoder Architecture

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Decoding performance of binary and non-binary LDPC codes for IEEE 802.11n standard

2012 International Conference on Recent Trends in Information Technology ◽

10.1109/icrtit.2012.6206782 ◽

2012 ◽

Cited By ~ 4

Author(s):

P. Venkateshwari ◽

M. Anbuselvi

Keyword(s):

Ldpc Codes ◽

Ieee 802.11N

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Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2218839 ◽

2013 ◽

Vol 21 (9) ◽

pp. 1756-1761 ◽

Cited By ~ 15

Author(s):

Jun Lin ◽

Zhiyuan Yan

Keyword(s):

Ldpc Codes ◽

Decoder Architecture

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Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

Integration ◽

10.1016/j.vlsi.2019.04.005 ◽

2019 ◽

Vol 69 ◽

pp. 234-241

Author(s):

Huyen Pham Thi ◽

Hanho Lee ◽

Xuan Nghia Pham

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Nonbinary Ldpc Codes

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Performance of IEEE 802.11n LDPC codes

International Journal of Mathematical Analysis ◽

10.12988/ijma.2017.710138 ◽

2017 ◽

Vol 11 (22) ◽

pp. 1065-1073

Author(s):

Yenny Alexandra Avendano Martinez ◽

Octavio Jose Salcedo Parra ◽

Giovanny Mauricio Tarazona Bermudez

Keyword(s):

Error Detection ◽

High Performance ◽

Ldpc Codes ◽

Low Density ◽

Parity Check ◽

Ieee 802.11N ◽

Noise Environment ◽

Low Density Parity Check ◽

Parity Check Codes

LDPC (Low Density Parity Check Codes) is a set of algorithms that send, receive and correct in a noise environment, frames transmitted in a LAN environment. This article demonstrates the high performance of the LDPC in environments of noise, compared to the CRC error detection code highly currently implemented, in this way the efficiency of LDPC is shown specifically over the 802. 11n protocol.

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