scholarly journals Artificial neural networks as building blocks of mixed signal FPGA

2004 ◽  
Author(s):  
R. Manjunath ◽  
K.S. Gurumurthy
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Building Blocks ◽  
Mixed Signal ◽  
Artificial Neural

Compact building blocks for artificial neural networks

1999 ◽  
Vol 35 (1) ◽  
pp. 56 ◽  
Author(s):  
M. Meléndez-Rodríguez ◽  
J. Silva-Martínez
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Building Blocks ◽  
Artificial Neural

Synthetic Neuron Implementations

2011 ◽  
pp. 1555-1561
Author(s):  
Snorre Aunet
Keyword(s):  
Neural Networks ◽  
Signal Processing ◽  
Artificial Neural Networks ◽  
Supply Voltage ◽  
Neuron Models ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Signal Systems ◽  
Interesting Candidate ◽  
Artificial Neural

Many different synthetic neuron implementations exist, that include a variety of traits associated with biological neurons and our understanding of them. An important motivation behind the studies, modelling and implementations of different synthetic neurons, is that nature has provided the most efficient ways of doing important types of computations, that we are trying to mimick. Whether it is Artificial Neural Networks (ANNs) or other mixed signal systems, technology has always evolved in the direction of lower energy per unit computation ( Mead, 1990 ). Simple Neuron models as threshold elements, or perceptrons, are promising candidates for implementing future signal processing systems, including CMOS and SET ( Schmid & Leblebici, 2003 ), ( Beiu & Ibrahim, 2007 ). In this article a small number of published subthreshold, ultra low power, perceptrons / threshold elements are compared regarding power consumption, operational speed and defect tolerance. The “mirrored” gate operating in subthreshold and combined with redundancy, might be an interesting candidate for implementing artificial neural networks as well as other mixed-signal processing circuitry. Previously unpublished results demonstrate the mirrored gate producing appropriate binary outputs at 180 mV supply voltage, even when a transistor was cut off the supply voltage, for a redundancy factor of 2, using shorted outputs, as in ( Aunet & Hartmann, 2003 ).

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