scholarly journals Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

2010 ◽  
Author(s):  
Antonin Hermanek ◽  
Michal Kunes ◽  
Milan Tichy
Keyword(s):  
Power Consumption ◽  
Reducing Power ◽  
Clock Gating ◽  
Embedded Dsp

Analysis of LED Backlight Design Based on Dynamic Regional Control Technology

2013 ◽  
Vol 739 ◽  
pp. 423-426
Author(s):  
De Yue Cao ◽  
Yi Zou
Keyword(s):  
Power Consumption ◽  
Reducing Power ◽  
Control Technology ◽  
Paper Briefly ◽  
Saving Energy ◽  
Regional Control ◽  
Consumption And Saving ◽  
Led Backlight

This paper briefly explains the advantages of LED and the classification of LED backlight and explores the pattern of LED backlight based on dynamic regional control technology to overcome and improve the inherent problems of LCD TV monitor on purpose of reducing power consumption and saving energy.

Reducing AES power consumption using clock gating

2021 ◽  
Author(s):  
Piotr Chodorowski ◽  
Zbigniew Szaszkowski
Keyword(s):  
Power Consumption ◽  
Clock Gating

Reducing Power Consumption in Memories

2002 ◽  
pp. 117-140
Author(s):  
Alexander Chatzigeorgiou ◽  
Spiridon Nikolaidis
Keyword(s):  
Power Consumption ◽  
Reducing Power

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

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