Reducing AES power consumption using clock gating

2021 ◽  
Author(s):  
Piotr Chodorowski ◽  
Zbigniew Szaszkowski
Keyword(s):  
Power Consumption ◽  
Clock Gating

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

scholarly journals HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2457
Author(s):  
Hui Xu ◽  
Zehua Peng ◽  
Huaguo Liang ◽  
Zhengfeng Huang ◽  
Cong Sun ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Feedback Loop ◽  
Low Cost ◽  
Low Power Consumption ◽  
Clock Gating ◽  
Single Node ◽  
Area Overhead ◽  
Power Delay Product ◽  
Reduced Power Consumption

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

An Improved VLSI design of ALU based FIR Filter for Biomedical Image Filtering Application

2020 ◽  
Vol 16 ◽  
Author(s):  
M. Arulkumar ◽  
M. Chandrasekaran
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Impulse Response ◽  
High Speed ◽  
Image Filtering ◽  
Fir Filter ◽  
Vlsi Circuit ◽  
Clock Gating ◽  
Booth Multiplier ◽  
Ripple Carry Adder

Aim: FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder. Objective: The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators. Introduction: In the field of VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block's usage is increased it consumes much power. Method: The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses full adder circuit for its operation. It propagates the carry value in last bit. For addition, the combination of CSA and RCA utilizes less area, high speed and provides the better through put. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach on medical field. Results: Thus, the design and analysis of proposed ALU based FIR filter with latch-based clock gating technique is designed and analyzed various parameters. Here the modified adders and multiplier is proposed for efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders' performance. The enhanced booth multiplier is designed using add and shift method for reducing the number of stages to calculate the result. This process is applied to perform image processing of retina image. After designing the ALU based FIR filter structure in VLSI environment, the image is loaded on the MATLAB as the .png format then it is converted into hex file, which is read from the Xilinx to perform filtering the process. Then the 'dataout' is converted into binary file to obtain the result of filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch- based design for reducing the dynamic and clock power consumption. The number of adder's circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system. Conclusion: Thus the proposed methodology concluded that design and analysis of ALU based FIR filter for medical image processing gives the efficient result on the way of achieving the factors such that power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained the better result than the existing VLSI based image processing works. The Latch- based clock gating circuit is connected with the proposed circuit, based on the gated clock signal it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB with the adaptation of 2018a tool, the image filtering was done.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 342-350
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

Design of Digital Operational Units with Low Power Consumption

2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Digital Design ◽  
Low Power Consumption ◽  
Structural Description ◽  
Clock Gating ◽  
Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

A SAT-Based Methodology for Effective Clock Gating for Power Minimization

2018 ◽  
Vol 28 (01) ◽  
pp. 1950011
Author(s):  
Khushbu Chandrakar ◽  
Suchismita Roy
Keyword(s):  
Power Consumption ◽  
Optimization Techniques ◽  
Total Power ◽  
Clock Signal ◽  
Clock Gating ◽  
Clock Tree ◽  
Synchronous Circuits ◽  
Design And Optimization ◽  
Total Power Consumption ◽  
On Chip

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

scholarly journals Clock Gating Flip-Flop using Embedded XoR Circuitry

2021 ◽  
Author(s):  
Peiyi Zhao ◽  
William Cortes ◽  
Congyi Zhu ◽  
Tom Springer
Keyword(s):  
Power Consumption ◽  
Switching Activity ◽  
Clock Gating ◽  
Flip Flop ◽  
Dynamic Power ◽  
Data Switching

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.

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