Power reduction techniques for Dynamically Reconfigurable Processor Arrays

2008 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2008.4629949 ◽

2008 ◽

Cited By ~ 15

Author(s):

T. Nishimura ◽

K. Hirai ◽

Y. Saito ◽

T. Nakamura ◽

Y. Hasegawa ◽

...

Keyword(s):

Power Reduction ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Reduction Techniques ◽

Processor Arrays

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Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells

2009 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2009.5377641 ◽

2009 ◽

Cited By ~ 5

Author(s):

Kei'ichiro Hirai ◽

Masaru Kato ◽

Yoshiki Saito ◽

Hideharu Amano

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Coarse Grained ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Processor Arrays

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Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique

2008 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2008.4762410 ◽

2008 ◽

Cited By ~ 12

Author(s):

Yoshiki Saito ◽

Tomoaki Shirai ◽

Takuro Nakamura ◽

Takashi Nishimura ◽

Yohei Hasegawa ◽

...

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Coarse Grained ◽

Power Gating ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Fine Grained ◽

Processor Arrays

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Quantitative comparison of the power reduction techniques for samsung reconfigurable processor

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865490 ◽

2014 ◽

Cited By ~ 1

Author(s):

Hoyoung Kim ◽

Soojung Ryu ◽

Abhishek Sinkar ◽

Nam Sung Kim

Keyword(s):

Power Reduction ◽

Quantitative Comparison ◽

Reconfigurable Processor ◽

Reduction Techniques

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Design Methodology and Trade-Offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays

2007 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2007.4380771 ◽

2007 ◽

Cited By ~ 4

Author(s):

Yohei Hasegawa ◽

Satoshi Tsutsumi ◽

Vasutan Tanbunheng ◽

Takuro Nakamura ◽

Takashi Nishimura ◽

...

Keyword(s):

Design Methodology ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Processor Arrays ◽

Trade Offs

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A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays

IEICE Transactions on Information and Systems ◽

10.1093/ietisy/e91-d.11.2655 ◽

2008 ◽

Vol E91-D (11) ◽

pp. 2655-2665 ◽

Cited By ~ 2

Author(s):

V. TUNBUNHENG ◽

H. AMANO

Keyword(s):

Graph Representation ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Processor Arrays ◽

Retargetable Compiler

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Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays

2007 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2007.4439264 ◽

2007 ◽

Cited By ~ 4

Author(s):

Satoshi Tsutsumi ◽

Vasutan Tunbunheng ◽

Yohei Hasegawa ◽

Adepu Parimala ◽

Takuro Nakamura ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Processor Arrays ◽

Configuration Scheme

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Area and power reduction techniques for time-based image sensor pixel design

2009 International Conference on Microelectronics - ICM ◽

10.1109/icm.2009.5418593 ◽

2009 ◽

Cited By ~ 3

Author(s):

Daniel Matolin ◽

Christoph Posch ◽

Rainer Wohlgenannt

Keyword(s):

Image Sensor ◽

Power Reduction ◽

Reduction Techniques

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Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681431 ◽

2010 ◽

Cited By ~ 1

Author(s):

Kazuei Hironaka ◽

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

...

Keyword(s):

Power Consumption ◽

Reducing Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

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Implementation of dynamically reconfigurable processor DAPDNA-2

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500086 ◽

2005 ◽

Cited By ~ 21

Author(s):

T. Sato ◽

H. Watanabe ◽

K. Shiba

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005. ◽

10.1109/fpt.2005.1568541 ◽

2006 ◽

Cited By ~ 11

Author(s):

Y. Hasegawa ◽

S. Abe ◽

H. Matsutani ◽

H. Amano ◽

K. Anjo ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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