A layered QC-LDPC decoder architecture for high speed communication system

2012 ◽  
Author(s):  
Chiu-Wing Sham ◽  
Xu Chen ◽  
Wai M. Tam ◽  
Yue Zhao ◽  
Francis C.M. Lau
Keyword(s):  
Communication System ◽  
High Speed ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

2019 ◽  
Vol 37 (3) ◽  
pp. 515-522
Author(s):  
Tianjiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Fpga Implementation ◽  
Maximum Frequency ◽  
Ldpc Decoder ◽  
Memory Strategies ◽  
Multiple Data ◽  
Decoder Architecture ◽  
Place And Route ◽  
Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

scholarly journals LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

2019 ◽  
Vol 37 (2) ◽  
pp. 299-307 ◽  
Author(s):  
TianJiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Ldpc Codes ◽  
The State ◽  
Elementary Transformation ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Art Works ◽  
Decoder Architecture ◽  
Lower Triangular

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

High-Speed Architectures for Parallel BCH Decoders

2014 ◽  
Vol 496-500 ◽  
pp. 2269-2273
Author(s):  
Wei Liu ◽  
Li Feng Zhao
Keyword(s):  
Iterative Method ◽  
Communication System ◽  
Digital Technology ◽  
High Speed ◽  
Error Correcting Codes ◽  
Vlsi Implementation ◽  
Bch Codes ◽  
New Method ◽  
Decoder Architecture

Bose-Chaudhuri-Hocquenghen (BCH) error-correcting codes are now widely used in communication system and digital technology. The original iterative method is complex and time-consuming operations. An inversion less decoding method for binary BCH codes was proposed to simplify the Berlekamp-Massey algorithm, which can eliminate the bottleneck in long BCH decoder. For our considered parallel decoder architecture, the simplicity of this new method makes a simplified VLSI implementation possible.

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

scholarly journals Prototype Design and Experimental Evaluation of Autonomous Collaborative Communication System for Emerging Maritime Use Cases

Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3871
Author(s):  
Jiri Pokorny ◽  
Khanh Ma ◽  
Salwa Saafi ◽  
Jakub Frolka ◽  
Jose Villa ◽  
...  
Keyword(s):  
Communication System ◽  
Autonomous Vehicles ◽  
High Speed ◽  
High Capacity ◽  
Workplace Safety ◽  
Unmanned Vehicles ◽  
Use Cases ◽  
Automated Systems ◽  
Collaborative Communication ◽  
Wide Range

Automated systems have been seamlessly integrated into several industries as part of their industrial automation processes. Employing automated systems, such as autonomous vehicles, allows industries to increase productivity, benefit from a wide range of technologies and capabilities, and improve workplace safety. So far, most of the existing systems consider utilizing one type of autonomous vehicle. In this work, we propose a collaboration of different types of unmanned vehicles in maritime offshore scenarios. Providing high capacity, extended coverage, and better quality of services, autonomous collaborative systems can enable emerging maritime use cases, such as remote monitoring and navigation assistance. Motivated by these potential benefits, we propose the deployment of an Unmanned Surface Vehicle (USV) and an Unmanned Aerial Vehicle (UAV) in an autonomous collaborative communication system. Specifically, we design high-speed, directional communication links between a terrestrial control station and the two unmanned vehicles. Using measurement and simulation results, we evaluate the performance of the designed links in different communication scenarios and we show the benefits of employing multiple autonomous vehicles in the proposed communication system.

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