On bit-serial packet routing for the mesh and the torus

Division and bit-serial multiplication over GF(qm)

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1992.0036 ◽

1992 ◽

Vol 139 (3) ◽

pp. 230 ◽

Cited By ~ 27

Author(s):

M.A. Hasan ◽

V.K. Bhargava

Keyword(s):

Bit Serial

Download Full-text

Bit-serial systolic sorting: general complexities and an implementation in VLSI

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1987.0022 ◽

1987 ◽

Vol 134 (3) ◽

pp. 125

Author(s):

H.F. Li ◽

R. Jayakumar ◽

X. Sun

Keyword(s):

Bit Serial

Download Full-text

Spectrum Based Power Management for Congested IoT Networks

Sensors ◽

10.3390/s21082681 ◽

2021 ◽

Vol 21 (8) ◽

pp. 2681

Author(s):

Kedir Mamo Besher ◽

Juan Ivan Nieto-Hipolito ◽

Raymundo Buenrostro-Mariscal ◽

Mohammed Zamshed Ali

Keyword(s):

Power Management ◽

Network Performance ◽

Channel Allocation ◽

Battery Life ◽

Packet Routing ◽

Data Packets ◽

Increasing Demand ◽

Iot Devices ◽

Set Up

With constantly increasing demand in connected society Internet of Things (IoT) network is frequently becoming congested. IoT sensor devices lose more power while transmitting data through congested IoT networks. Currently, in most scenarios, the distributed IoT devices in use have no effective spectrum based power management, and have no guarantee of a long term battery life while transmitting data through congested IoT networks. This puts user information at risk, which could lead to loss of important information in communication. In this paper, we studied the extra power consumed due to retransmission of IoT data packet and bad communication channel management in a congested IoT network. We propose a spectrum based power management solution that scans channel conditions when needed and utilizes the lowest congested channel for IoT packet routing. It also effectively measured power consumed in idle, connected, paging and synchronization status of a standard IoT device in a congested IoT network. In our proposed solution, a Freescale Freedom Development Board (FREDEVPLA) is used for managing channel related parameters. While supervising the congestion level and coordinating channel allocation at the FREDEVPLA level, our system configures MAC and Physical layer of IoT devices such that it provides the outstanding power utilization based on the operating network in connected mode compared to the basic IoT standard. A model has been set up and tested using freescale launchpads. Test data show that battery life of IoT devices using proposed spectrum based power management increases by at least 30% more than non-spectrum based power management methods embedded within IoT devices itself. Finally, we compared our results with the basic IoT standard, IEEE802.15.4. Furthermore, the proposed system saves lot of memory for IoT devices, improves overall IoT network performance, and above all, decrease the risk of losing data packets in communication. The detail analysis in this paper also opens up multiple avenues for further research in future use of channel scanning by FREDEVPLA board.

Download Full-text

Six shades lighter: a bit-serial implementation of the AES family

Journal of Cryptographic Engineering ◽

10.1007/s13389-021-00265-8 ◽

2021 ◽

Author(s):

Sergio Roldán Lombardía ◽

Fatih Balli ◽

Subhadeep Banik

Keyword(s):

Block Cipher ◽

Block Ciphers ◽

Authenticated Encryption ◽

Current Standard ◽

Asic Circuit ◽

The Family ◽

Encryption And Decryption ◽

Preliminary Version ◽

Reduction In Area ◽

Bit Serial

AbstractRecently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

Download Full-text