A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard

2007 ◽  
Author(s):  
Mehran Mozaffari-Kermani ◽  
Arash Reyhani-Masoleh
Keyword(s):  
Fault Detection ◽  
Advanced Encryption Standard ◽  
Hardware Implementations

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

2019 ◽  
Vol 29 (03) ◽  
pp. 2050044
Author(s):  
Noura Benhadjyoussef ◽  
Mouna Karmani ◽  
Mohsen Machhout ◽  
Belgacem Hamdi
Keyword(s):  
Fault Detection ◽  
Fault Analysis ◽  
Advanced Encryption Standard ◽  
Implementation Cost ◽  
Additional Time ◽  
Area Overhead ◽  
Differential Fault Analysis ◽  
Detection Capabilities ◽  
Xilinx Fpga ◽  
Detection Schemes

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

scholarly journals A Robust Fault Detection Scheme for the Advanced Encryption Standard

2013 ◽  
Vol 5 (6) ◽  
pp. 49-55 ◽  
Author(s):  
Hassen Mestiri ◽  
Noura Benhadjyoussef ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Fault Detection ◽  
Advanced Encryption Standard ◽  
Detection Scheme ◽  
Robust Fault Detection

scholarly journals A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm Using Verilog HDL

2021 ◽  
Vol 9 (VII) ◽  
pp. 1876-1879
Author(s):  
Charrith Srinivaas
Keyword(s):  
Advanced Encryption Standard ◽  
Verilog Hdl ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Rapid Pace ◽  
Tools And Techniques ◽  
Day By Day

As the technology is getting more and more advanced day by day in a rapid pace the problem for the security of data is also increasing at a very staggering rate. The hackers are equipped with new advanced tools and techniques to break any security system. Hence people are getting even more concerned about their data and data’s security. The data security can be achieved by either software or hardware implementations or both put together working in harmony. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide and have far greater more efficiency. This work mainly focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm which is the most highly used algorithm for Encryption. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and therefore the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work Mainly discusses the design implementation of the AES algorithm and the resources which are consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows- Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer.

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