Estimating Soft Processor Soft Error Sensitivity through Fault Injection

2015 ◽  
Author(s):  
Nathan A. Harward ◽  
Michael R. Gardiner ◽  
Luke W. Hsiao ◽  
Michael J. Wirthlin
Keyword(s):  
Fault Injection ◽  
Soft Error ◽  
Error Sensitivity

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

2012 ◽  
Vol 61 (3) ◽  
pp. 313-322 ◽  
Author(s):  
Luis Entrena ◽  
Mario Garcia-Valderas ◽  
Raul Fernandez-Cardenal ◽  
Almudena Lindoso ◽  
Marta Portela ◽  
...  
Keyword(s):  
Fault Injection ◽  
Soft Error ◽  
Error Sensitivity ◽  
Sensitivity Evaluation

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

scholarly journals Evaluating the soft error sensitivity of a GPU-based SoC for matrix multiplication

2020 ◽  
Vol 114 ◽  
pp. 113856
Author(s):  
Germán León ◽  
José M. Badía ◽  
Jose A. Belloch ◽  
Almudena Lindoso ◽  
Luis Entrena
Keyword(s):  
Matrix Multiplication ◽  
Soft Error ◽  
Error Sensitivity

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

2016 ◽  
pp. 277-305
Author(s):  
Qiang Guan ◽  
Nathan DeBardeleben ◽  
Sean Blanchard ◽  
Song Fu ◽  
Claude H. Davis IV ◽  
...  
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Soft Errors ◽  
Small Degree ◽  
Soft Error ◽  
Power Efficient ◽  
Fine Grained ◽  
Different Characteristics ◽  
The Impact ◽  
Performance Computing

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

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