Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) ◽

10.1109/fccm.2005.52 ◽

2005 ◽

Cited By ~ 6

Author(s):

H. Amano ◽

S. Abe ◽

Y. Hasegawa ◽

K. Deguchi ◽

M. Suzuki

Keyword(s):

Cost Analysis ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681431 ◽

2010 ◽

Cited By ~ 1

Author(s):

Kazuei Hironaka ◽

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

...

Keyword(s):

Power Consumption ◽

Reducing Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

Implementation of dynamically reconfigurable processor DAPDNA-2

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500086 ◽

2005 ◽

Cited By ~ 21

Author(s):

T. Sato ◽

H. Watanabe ◽

K. Shiba

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005. ◽

10.1109/fpt.2005.1568541 ◽

2006 ◽

Cited By ~ 11

Author(s):

Y. Hasegawa ◽

S. Abe ◽

H. Matsutani ◽

H. Amano ◽

K. Anjo ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502438 ◽

2018 ◽

Cited By ~ 7

Author(s):

Taro Fujii ◽

Takao Toi ◽

Teruhito Tanaka ◽

Katsumi Togawa ◽

Toshiro Kitaoka ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

New Generation

Download Full-text

Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme

2012 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2012.6407083 ◽

2012 ◽

Cited By ~ 2

Author(s):

Yoshichika Fujioka ◽

Michitaka Kameyama

Keyword(s):

Data Transfer ◽

Size Reduction ◽

Transfer Scheme ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Memory Size ◽

Packet Data ◽

Download Full-text

Low power image processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array

2009 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2009.5377614 ◽

2009 ◽

Cited By ~ 2

Author(s):

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

Vasutan Tunbunheng ◽

...

Keyword(s):

Image Processing ◽

Low Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines ◽

10.1109/fccm.2004.42 ◽

2004 ◽

Cited By ~ 6

Author(s):

N. Suzuki ◽

S. Kurotaki ◽

M. Suzuki ◽

N. Kaneko ◽

Y. Yamada ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

MuCCRA-3: A low power dynamically Reconfigurable Processor Array

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419853 ◽

2010 ◽

Cited By ~ 2

Author(s):

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

Vasutan Tunbunheng ◽

Yoshihiro Yasuda ◽

...

Keyword(s):

Low Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

Download Full-text

Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor

2012 IEEE 6th International Symposium on Embedded Multicore SoCs ◽

10.1109/mcsoc.2012.35 ◽

2012 ◽

Cited By ~ 5

Author(s):

Hideharu Amano ◽

Masayuki Kimura ◽

Nobuaki Ozaki

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Context Memory

Download Full-text

A Dynamically Reconfigurable Processor with Multi-Mode Operation Based on Newly Developed Full-Adder/D-Flip-Flop Merged Module (FDMM)

10.7567/ssdm.2000.e-3-4 ◽

2000 ◽

Author(s):

Satoshi SAKAIDANI ◽

Naoto MIYAMOTO ◽

Tadahiro OHMI

Keyword(s):

Full Adder ◽

Flip Flop ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable ◽

Mode Operation ◽

Multi Mode

Download Full-text