Co-Simulation of Self-Adaptive Automotive Embedded Systems

Author(s):  
Marc Zeller ◽  
Gereon Weiss ◽  
Dirk Eilers ◽  
Rudi Knorr
2006 ◽  
Vol 2006 ◽  
pp. 1-15 ◽  
Author(s):  
Thilo Streichert ◽  
Dirk Koch ◽  
Christian Haubelt ◽  
Jürgen Teich

Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Jouni Isoaho ◽  
Hannu Tenhunen

The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.


2006 ◽  
Vol 2006 (1) ◽  
pp. 042168 ◽  
Author(s):  
Thilo Streichert ◽  
Dirk Koch ◽  
Christian Haubelt ◽  
Jürgen Teich

2007 ◽  
Vol 2 (1) ◽  
pp. 29-36
Author(s):  
Thilo Streichert ◽  
Christian Strengert ◽  
Dirk Koch ◽  
Christian Haubelt ◽  
Jürgen Teich

In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the applicability, an implementation on a network of FPGA-based boards.


Sign in / Sign up

Export Citation Format

Share Document