A low-cost susceptibility analysis methodology to selectively harden logic circuits

Author(s):  
I. Wali ◽  
B. Deveautour ◽  
A. Virazel ◽  
A. Bosio ◽  
P. Girard ◽  
...  
2016 ◽  
Vol 16 (2) ◽  
pp. 103-118 ◽  
Author(s):  
Agata Żółtaszek ◽  
Renata Pisarek

Abstract National airlines operate in a highly competitive environment. EU airlines face a challenge to compete with low cost carriers, as a result of the liberalization process in the sector. European flag airlines of non-EU member states, not benefiting from liberalization, are forced to compete internationally. This research is focused on national carriers, as they provide the majority of service to and from central and regional airports. Therefore, to establish the most efficient entities on the passenger air transport market, DEA (Data Envelopment Analysis) methodology, has been utilized. The purpose of this paper is to evaluate the effectiveness of 29 chosen national airlines in Europe in the year 2013, using the DEA approach, to pinpoint the subset of fully-efficient market leaders, as well as potential sources of inefficiency, among less effective carriers. The analysis incorporates information on inputs (e.g. fleet, number of employees, number of countries and airports served) and outputs (revenue, annual passengers carried, load factor). The results show that more than 40% (12 of 29) researched airlines are effective and the other 34% are near-efficient. Moreover, outcomes suggest that “going big” may not increase effectiveness. It is harder to achieve full efficiency for big carriers than small ones.


2017 ◽  
Vol 33 (1) ◽  
pp. 25-36 ◽  
Author(s):  
I. Wali ◽  
B. Deveautour ◽  
Arnaud Virazel ◽  
A. Bosio ◽  
P. Girard ◽  
...  
Keyword(s):  
Low Cost ◽  

1998 ◽  
Vol 514 ◽  
Author(s):  
Simon Yang

ABSTRACTInterconnect delay is believed to have a dominating impact on the speed of large logic circuits (such as micro-processors) when the Si technology is scaled into sub- 0.25um generations. In this paper, we analyzed interconnect scaling issues based on leading micro-processor trend data, simple RC delay model and the “Rents' rule”. It was concluded that, in order to not limit the speed of large logic circuits, “fat” metal wires need to be used for upper metal layers, which will lead to a rapid increase of required number of metal layers (>10) for sub-0.25um technology generations. Introducing Cu and low ε interconnect system can delay this rapid increase by ∼1 generation. Creating multiple clock frequencies in large logic chips and reducing the size of high frequency islands appears effective in containing the interconnection delay problem. Therefore, the proposed interconnection scaling/development strategy is to introduce Cu and low ε dielectric into manufacturing in next 1∼3 generation (0.25um∼0.13um), develop low cost and high yield interconnect system to enable ∼10 interconnect layers, and improve circuit design methodology to reduce high frequency island size.


Nanophotonics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1547-1558 ◽  
Author(s):  
Vincenzo Ardizzone ◽  
Luisa De Marco ◽  
Milena De Giorgi ◽  
Lorenzo Dominici ◽  
Dario Ballarini ◽  
...  

AbstractTwo-dimensional semiconductors are considered intriguing materials for photonic applications, thanks to their stunning optical properties and the possibility to manipulate them at the nanoscale. In this review, we focus on transition metal dichalcogenides and low-dimensional hybrid organic-inorganic perovskites, which possess the same characteristics related to planar confinement of their excitons: large binding energies, wide exciton extension, and high oscillator strength. We describe their optoelectronic properties and their capability to achieve strong coupling with light, with particular attention to polariton-polariton interactions. These aspects make them very attractive for polaritonic devices working at room temperature, in view of the realization of all-optical logic circuits in low-cost and easy-to-synthesize innovative materials.


2019 ◽  
Vol 1 (4) ◽  
pp. 625-636 ◽  
Author(s):  
Bing Yang ◽  
Gang He ◽  
Li Zhu ◽  
Chong Zhang ◽  
Yongchun Zhang ◽  
...  
Keyword(s):  
Low Cost ◽  

2017 ◽  
Vol 51 ◽  
pp. 209-219 ◽  
Author(s):  
Jorge Tonfat ◽  
Lucas Tambara ◽  
André Santos ◽  
Fernanda Lima Kastensmidt

2021 ◽  
Vol 2131 (4) ◽  
pp. 042070
Author(s):  
N P Voronova

Abstract The article provides a brief analysis of the starting processes of electrical devices in autonomous systems of limited power. The existing methods of automatic start-up and regulation of the operation of electrical machines and apparatus are considered, which are a multi-link system, the reliability of which is determined by a number of intermediate links, and the stepping is one of the biggest drawbacks that negatively affect the dynamics of the starting process. In addition, the issues of simplicity, low cost and small dimensions of the automatic control system for electrical installations are of particular importance in the problem of energy saving. The use of low-power thermistors as part of starting devices requires intermediate equipment and various components, which significantly reduces the reliability of the equipment. The increase in currents flowing through the ballasts simplifies the electrical control and regulation circuits. For the use of polycrystalline semiconductor thermistors in circuits with high currents, it is necessary to use special designs in order to prevent overheating of the thermistor material. The article provides algorithms for the synthesis of starting rheostats. A number of restrictions are considered and formulated, on which the nature of the processes of starting electric motors with the help of thermistor rheostats, which ensure the fulfillment of certain restrictions, depends. Recommendations are given for the formation of optimal starting processes using rheostats built on semiconductor polycrystalline thermistors.


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