A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture

2011 ◽  
Author(s):  
I. Voyiatzis ◽  
C. Efstathiou ◽  
H. Antonopoulou
Keyword(s):  
Input Vector ◽  
Sram Cell

A New Approach for SRAM Soft Defect Root Cause Identification

2007 ◽  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger
Keyword(s):  
Integrated Circuits ◽  
Top Down ◽  
Feature Size ◽  
Design Rules ◽  
New Approach ◽  
Root Cause ◽  
Wafer Fab ◽  
Sram Cell ◽  
Tcad Simulation ◽  
Root Cause Identification

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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