Design methodologies and tools for circuit design in CMOS nanometer technologies

2006 ◽  
Author(s):  
Georges Gielen
Keyword(s):  
Circuit Design ◽  
Design Methodologies

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

Systematic Circuit Design Methodologies with Layout Considerations

2020 ◽  
pp. 123-153
Author(s):  
Fábio Passos ◽  
Elisenda Roca ◽  
Rafael Castro-López ◽  
Francisco V. Fernández
Keyword(s):  
Circuit Design ◽  
Design Methodologies
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