Technology impacts on sub-90nm CMOS circuit design & design methodologies

Author(s):  
R. Puri ◽  
T. Karnik ◽  
R. Joshi
2020 ◽  
Author(s):  
Neelam Swami ◽  
Bhupen Khatri

2015 ◽  
Vol E98.C (1) ◽  
pp. 35-44 ◽  
Author(s):  
Korkut Kaan TOKGOZ ◽  
Kimsrun LIM ◽  
Seitarou KAWAI ◽  
Nurul FAJRI ◽  
Kenichi OKADA ◽  
...  

Integration ◽  
2009 ◽  
Vol 42 (1) ◽  
pp. 1-2
Author(s):  
R. Castro-López ◽  
D. Rodríguez de Llera ◽  
M. Ismail ◽  
F.V. Fernández

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).


2004 ◽  
Vol 151 (2) ◽  
pp. 167 ◽  
Author(s):  
A.J. Scholten ◽  
L.F. Tiemeijer ◽  
R. van Langevelde ◽  
R.J. Havens ◽  
A.T.A. Zegers-van Duijnhoven ◽  
...  
Keyword(s):  
Rf Cmos ◽  

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