scholarly journals A low power all-digital signal component separator for uneven multi-level LINC systems

2011 ◽  
Author(s):  
Tsan-Wen Chen ◽  
Ping-Yuan Tsai ◽  
Dieter De Moitie ◽  
Jui-Yuan Yu ◽  
Chen-Yi Lee
Keyword(s):  
Low Power ◽  
Digital Signal ◽  
Signal Component ◽  
Multi Level

Low-Power Digital Signal Processing Using Approximate Adders

2013 ◽  
Vol 32 (1) ◽  
pp. 124-137 ◽  
Author(s):  
Vaibhav Gupta ◽  
Debabrata Mohapatra ◽  
Anand Raghunathan ◽  
Kaushik Roy
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

scholarly journals Reversible logic in pipelined low power vedic multiplier

2019 ◽  
Vol 16 (3) ◽  
pp. 1265
Author(s):  
Ansiya Eshack ◽  
S. Krishnakumar
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Large Scale ◽  
Optical Computing ◽  
Digital Signal ◽  
Logic Gates ◽  
Reversible Logic ◽  
Large Scale Integration ◽  
Time Required ◽  
Scale Integration

<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

scholarly journals Baseband I/Q regeneration Method for Direct Conversion Receiver to nullify effect of I/Q mismatch

2016 ◽  
Vol 5 (3) ◽  
pp. 50 ◽  
Author(s):  
M. Shah ◽  
S. Gupta
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal ◽  
Direct Conversion ◽  
Performance Degradation ◽  
Wireless Receiver ◽  
Novel Method ◽  
The One

Direct Conversion Receiver is the choice of the today’s designer for low power compact wireless receiver. DCR is attractive due to low power, small size and highly monolithic integratable structure, but distortions affect its performance.  I/Q mismatch is the one of the major distortion which is responsible for performance degradation.  In this paper, a novel method for Direct Conversion Receiver is suggested, which makes it insensitive to the I/Q mismatch. Here the classical homodyne architecture is modified to nullify effect of I/Q mismatch. The proposed method can be implemented in the Digital Signal Processing (DSP) back-end section also.  This feature makes it acceptable in the already designed/functioning classical homodyne architecture based receiver.

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