An Ultra Low-Noise CMOS Operational Amplifier with Programmable Noise-Power Trade-Off

2006 ◽  
Author(s):  
Carsten Bronskowski ◽  
Dietmar Schroeder
Keyword(s):  
Operational Amplifier ◽  
Low Noise ◽  
Noise Power ◽  
Trade Off ◽  
Ultra Low Noise ◽  
Power Trade

Design of ultra-low noise power system for high-precision detectors

2016 ◽  
Author(s):  
Jian-min Wang ◽  
Hong-fei Zhang ◽  
Sheng-zhao Lin ◽  
Yi Feng ◽  
Dong-xu Yang ◽  
...  
Keyword(s):  
Power System ◽  
High Precision ◽  
Low Noise ◽  
Noise Power ◽  
Ultra Low Noise

Design of high gain, high bandwidth neural amplifier IC considering noise-power trade-off

2018 ◽  
Author(s):  
N. M. Laskar ◽  
K. Guha ◽  
S. Nath ◽  
S. Chanda ◽  
K. L. Baishnab ◽  
...  
Keyword(s):  
High Gain ◽  
Noise Power ◽  
Trade Off ◽  
High Bandwidth ◽  
Power Trade

scholarly journals A High-Voltage and Low-Noise Power Amplifier for Driving Piezoelectric Stack Actuators

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6528
Author(s):  
Lisong Xu ◽  
Hongwen Li ◽  
Pengzhi Li ◽  
Chuan Ge
Keyword(s):  
Feedback Control ◽  
Power Amplifier ◽  
High Voltage ◽  
Operational Amplifier ◽  
High Performance ◽  
Low Cost ◽  
Low Noise ◽  
Noise Power ◽  
Novel Structure ◽  
Voltage Feedback

In this paper, based on the principles of general operational amplifiers, a high-voltage operational amplifier is developed. Considering the influences of piezoelectric stack actuators on the circuit, a novel structure using the high-voltage operational amplifier as a noninverting amplifier is proposed. Because of the simple circuit principles and the voltage feedback control structure, the proposed power amplifier has the advantages of low noise and small size, and it can be realized by discrete electric elements easily. In the application of precision positioning, a power amplifier using the proposed circuit principles for driving piezoelectric stack actuators is designed, simulated, and tested. The simulated results show that the proposed power amplifier could conform to the theory of the circuit. The experimental results show that the designed power amplifier conforms to the simulation, the bandwidth of the power amplifier is about 57 kHz, and the ripple of the power amplifier is less than 2 mV. Furthermore, the output of the proposed power amplifier maintains the same type of wave within in a large range of frequency, while the input is the sinusoidal or square wave, and the resolution of the mechanism which the power amplifier is applied in is about 4.5 nm. By selecting the critical electronic elements and using feedback control, the proposed circuit structure is able to realize a low-cost and high-performance power amplifier to drive piezoelectric stack actuators flexibly, which is the novel work of the paper.

scholarly journals Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3683
Author(s):  
Linkun Wu ◽  
David San Segundo Bello ◽  
Philippe Coppejans ◽  
Jan Craninckx ◽  
Andreas Süss ◽  
...  
Keyword(s):  
High Speed ◽  
Low Noise ◽  
System Level ◽  
Noise Power ◽  
Memory Bank ◽  
Trade Off ◽  
Burst Mode ◽  
Analysis And Design ◽  
Ultra High Speed

This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−.

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