Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package

2008 ◽  
Author(s):  
Yue Ying Ong ◽  
Kripesh Vaidyanathan ◽  
Soon Wee Ho ◽  
Vasarla Nagendra Sekhar ◽  
Ming Ching Jong ◽  
...  
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Low K

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

A novel polymer technology for underfill

2012 ◽  
Vol 1428 ◽  
Author(s):  
Osamu Suzuki ◽  
Toshiyuki Sato ◽  
Paul Czubarow ◽  
David Son
Keyword(s):  
Flip Chip ◽  
Mechanical Analysis ◽  
Reliability Testing ◽  
Hybrid Polymer ◽  
Scanning Calorimetry ◽  
Inorganic Hybrid ◽  
Fine Pitch ◽  
Capillary Type ◽  
Tin Silver Copper ◽  
Low K

AbstractCapillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology.Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. Given the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k/Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results.

UBM integrity studies on copper/low-k dielectrics for fine pitch flip chip packaging

2004 ◽  
Author(s):  
Seung Wook Yoon ◽  
V. Kripesh ◽  
Wong Wai Kwan ◽  
Li Chao Yong ◽  
Chen Man Tong ◽  
...  
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Flip Chip Packaging ◽  
Low K

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

2004 ◽  
Vol 33 (10) ◽  
pp. 1144-1155 ◽  
Author(s):  
Seung Wook Yoon ◽  
Vaidyanathan Kripesh ◽  
Su Young Ji Jeffery ◽  
Mahadevan K. Iyer
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Flip Chip Packaging ◽  
Low K

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package

2011 ◽  
Vol 1 (3) ◽  
pp. 279-290 ◽  
Author(s):  
Yue Ying Ong ◽  
Soon Wee Ho ◽  
Vasarla Nagendra Sekhar ◽  
Xuefen Ong ◽  
Jimmy Ong ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Study ◽  
Fine Pitch ◽  
Low K

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

2010 ◽  
Vol 50 (7) ◽  
pp. 986-994 ◽  
Author(s):  
Yue Ying Ong ◽  
Soon Wee Ho ◽  
Kripesh Vaidyanathan ◽  
Vasarla Nagendra Sekhar ◽  
Ming Chinq Jong ◽  
...  
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Low K
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