Distributed arithmetic LMS adaptive filter implementation without look-up table

2012 ◽  
Author(s):  
Anirut Trakultritrung ◽  
Ekkawin Thanangchusin ◽  
Sorawat Chivapreecha
Keyword(s):  
Adaptive Filter ◽  
Distributed Arithmetic ◽  
Look Up Table

scholarly journals FPGA based least mean square algorithm for noise cancellation in communication system

2018 ◽  
Vol 7 (3.3) ◽  
pp. 165
Author(s):  
Praveen Reddy ◽  
Dr Baswaraj Gadgay
Keyword(s):  
Adaptive Filter ◽  
Communication System ◽  
Noise Cancellation ◽  
Mean Square ◽  
Least Mean Square ◽  
Distributed Arithmetic ◽  
Negative Effect ◽  
Least Mean Square Algorithm ◽  
Design Comparison

We present modified Distributed Arithmetic (DA) based architecture for LMS Adaptive filter which has improved the throughput of the filter also area and power has been comparatively been reduced. As we know, the adaptive filter uses continuous recalculation and generation of new coefficients will generate the negative effect on the use of algorithm. We have used a special temporary LUT addressing technique has overcome the issues resulting in better performance and good results. In this paper, we have discussed about the adaptive filter and implementation of DA adaptive filter and also discussed the results obtained from the design. Comparison with traditional de-sign has also been done to show the effectiveness of the algorithm.   

scholarly journals FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

2010 ◽  
Vol 1 (1) ◽  
pp. 113-122
Author(s):  
Rajesh Kumar ◽  
Swapna Devi ◽  
S.S. Pattnaik
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Cost Effective ◽  
Fir Filter ◽  
Wireless Communication Systems ◽  
Effective Solution ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Look Up Table ◽  
The Look

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

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