Low-Temperature and Low-Pressure Cu-Cu Bonding by Pure Cu Nanosolder Paste for Wafer-Level Packaging

2017 ◽  
Author(s):  
Junjie Li ◽  
Tielin Shi ◽  
Xing Yu ◽  
Chaoliang Cheng ◽  
Jinhu Fan ◽  
...  
Keyword(s):  
Low Temperature ◽  
Low Pressure ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Cu Bonding ◽  
Pure Cu

scholarly journals The Effect of an Ag Nanofilm on Low-Temperature Cu/Ag-Ag/Cu Chip Bonding in Air

2021 ◽  
Vol 11 (20) ◽  
pp. 9444
Author(s):  
Yoonho Kim ◽  
Seungmin Park ◽  
Sarah Eunkyung Kim
Keyword(s):  
Low Temperature ◽  
High Performance ◽  
Bonding Process ◽  
Bonding Interface ◽  
Fine Pitch ◽  
Bonding Technology ◽  
Cu Bonding ◽  
Cu Oxidation ◽  
Pure Cu

Low-temperature Cu-Cu bonding technology plays a key role in high-density and high-performance 3D interconnects. Despite the advantages of good electrical and thermal conductivity and the potential for fine pitch patterns, Cu bonding is vulnerable to oxidation and the high temperature of the bonding process. In this study, chip-level Cu bonding using an Ag nanofilm at 150 °C and 180 °C was studied in air, and the effect of the Ag nanofilm was investigated. A 15-nm Ag nanofilm prevented Cu oxidation prior to the Cu bonding process in air. In the bonding process, Cu diffused rapidly to the bonding interface and pure Cu-Cu bonding occurred. However, some Ag was observed at the bonding interface due to the short bonding time of 30 min in the absence of annealing. The shear strength of the Cu/Ag-Ag/Cu bonding interface was measured to be about 23.27 MPa, with some Ag remaining at the interface. This study demonstrated the good bonding quality of Cu bonding using an Ag nanofilm at 150 °C.

scholarly journals Low-Temperature and Low-Pressure Cu–Cu Bonding by Highly Sinterable Cu Nanoparticle Paste

2017 ◽  
Vol 12 (1) ◽  
Author(s):  
Junjie Li ◽  
Xing Yu ◽  
Tielin Shi ◽  
Chaoliang Cheng ◽  
Jinhu Fan ◽  
...  
Keyword(s):  
Low Temperature ◽  
Low Pressure ◽  
Cu Nanoparticle ◽  
Cu Bonding

Low temperature and low pressure Cu-Cu bonding with Ag doped Cu nanosolder paste

2016 ◽  
Author(s):  
Junjie Li ◽  
Tielin Shi ◽  
Xing Yu ◽  
Chaoliang Cheng ◽  
Jinhu Fan ◽  
...  
Keyword(s):  
Low Temperature ◽  
Low Pressure ◽  
Cu Bonding

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

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