Forming a Vertical Interconnect Structure Using Dry Film Processing for Fan Out Wafer Level Packaging

2017 ◽  
Author(s):  
Yew Wing Leong ◽  
Hsiang Yao Hsiao ◽  
Soon Wee Ho ◽  
Boon Long Lau ◽  
Huamao Lin
Keyword(s):  
Wafer Level ◽  
Wafer Level Packaging ◽  
Film Processing ◽  
Vertical Interconnect ◽  
Dry Film

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 000079-000085 ◽  
Author(s):  
Michael Toepper ◽  
Tanja Braun ◽  
Robert Gernhardt ◽  
Martin Wilke ◽  
Piotr Mackowiak ◽  
...  
Keyword(s):  
Laser Scanning ◽  
New Technology ◽  
Side Wall ◽  
Wafer Level ◽  
Major Barrier ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Low K ◽  
Metallization Process ◽  
Dry Film

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

2012 ◽  
Vol 2012 (1) ◽  
pp. 000233-000238 ◽  
Author(s):  
Y. Lamy ◽  
S. Joblot ◽  
C. Ferrandon ◽  
J.F. Carpentier ◽  
G. Simon
Keyword(s):  
High Temperature ◽  
Low Cost ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
High Temperature Process ◽  
Bridge Approach ◽  
Different Diameters ◽  
Dry Film

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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