The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging

2014 ◽  
Author(s):  
Christine Hau-Riege ◽  
Beth Keser ◽  
Rey Alvarado ◽  
Ahmer Syed ◽  
YouWen Yau ◽  
...  
Keyword(s):  
Wafer Level ◽  
Wafer Level Packaging ◽  
Solder Balls ◽  
The Impact

Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000545-000566
Author(s):  
John Hunt ◽  
Adren Hsieh ◽  
Eddie Tsai ◽  
Chienfan Chen ◽  
Tsaiying Wang
Keyword(s):  
Temperature Cycling ◽  
Wafer Level ◽  
Development Activity ◽  
Wafer Level Packaging ◽  
First Case ◽  
Mask Design ◽  
To Come ◽  
And Performance ◽  
Reliability Performance ◽  
The Impact

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity. With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die. For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured. We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.

SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION

2012 ◽  
Vol 2012 (1) ◽  
pp. 000201-000208 ◽  
Author(s):  
Alberto Martins ◽  
Nelson Pinho ◽  
Harald Meixner
Keyword(s):  
Feedback Loop ◽  
High Volume ◽  
Data Availability ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Wafer Thickness ◽  
High Volume Production ◽  
Cte Mismatch ◽  
Volume Production ◽  
The Impact

NANIUM S.A. Portugal recently started producing eWLB fan-out [1][2] wafer level packaging technology on 300mm reconstituted wafers. Initial setup of this process demonstrated that the stable die Pick&Place accuracy plays a key role for product feasibility. In the subsequent volume production ramp-up it became apparent that the dynamic expansion of molded eWLB wafers, caused by thermal stress and CTE mismatch throughout the thin film redistribution and passivation layer up to bumping and reflow manufacturing processes requires a very tight die position monitoring over the complete wafer diameter. Feedback loop to the initial die placement and implementation of correction measures is essential to meet the quality and yield targets of different product configurations (die sizes, distance between dies, die thickness, wafer thickness, single die or system-inpackage) in high volume manufacturing. Stability and repeatability is of outermost importance. The paper will discuss the effects seen on the wafer, the monitoring and the strategies for feedback loop process enabling implementation of corrections into the reconstituted wafer before forming the artificial backend wafer by compression molding. The setup of adequate metrology steps throughout the process line supports the control of the various interlayer alignments. The end result is a centered process in the initial Pick&Place and various subsequent lithography steps (Stepper and Mask Aligner). Sustained data availability and processed data visualization made possible the development of an elaborate theoretical model enabling systematic optimizations of machine parameters and material expansion/compression correction factors. The model also permits the immediate visualization of the impact of each machine parameter on the global result.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

2017 ◽  
Vol 14 (4) ◽  
pp. 123-131 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Miniaturization of BAW devices and the impact of wafer level packaging technology

2013 ◽  
Author(s):  
Gernot Fattinger ◽  
Paul Stokes ◽  
Vishwavasu Potdar ◽  
Alexandre Volatier ◽  
Fabien Dumont ◽  
...  
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
The Impact

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000576-000583 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Electromigration Performance of WLPs with Standard and Polymer Core Balls

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002361-002392
Author(s):  
L. Nguyen ◽  
H. Nguyen ◽  
A. Prabhu
Keyword(s):  
Failure Modes ◽  
Void Formation ◽  
Solid Polymer ◽  
Current Crowding ◽  
Wafer Level ◽  
San Jose ◽  
Snagcu Solder ◽  
Wafer Level Packaging ◽  
Solder Balls ◽  
Board Level

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers. For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging
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